Yashashree_Wase_MEEE

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Information about Yashashree_Wase_MEEE

Published on November 30, 2016

Author: YashashreeWase

Source: slideshare.net

1. CMOS Image Sensor and Quanta Image Sensors: Past, Present and Future Presented by Yashashree Wase Electrical Engineering Contact: ywase@uidaho.edu Major Professor: James Frenzel, Ph.D., P.E. 111/29/2016 11:39 PM

2. Outline • Fundamentals of image sensors • Review of CCD and CMOS technology • Pixel architectures, widely commercialized pixels and comparison of pixel architectures • Comparison of CCD and CMOS image sensors • Applications and recent consumer products in the market • Introduction to Quanta Image Sensor • QIS progress review 11/29/2016 11:39 PM 2

3. Image Sensor 11/29/2016 11:39 PM 3 Fig. 1 Galaxy S5; a Samsung S5K2P2XX 1/2.6” sensor with an f/2.2 lens. Photo: iFixit Fig. 2 Typical Camera Modules on Mobile Phone Fig. 3 CMOS Image Sensor Chip

4. Image Sensor Roadmap 11/29/2016 11:39 PM 4 CCD was invented by Boyle and Smith at AT&T Bell Labs First Camera with built-in CCD CMOS APS Image Sensor at NASA/JPL by E.Fossum Worlds first fully digital photographic camera Quanta Image Sensor was conceived Quanta Image Sensor research began from 2012 to present 1950 1960 1970 1980 1990 2000 2010 2020 2030 MOS Photo-matrices 0th Generation Image Sensors Charge Coupled Devices 1st Generation Image Sensors CMOS ‘Camera On a Chip’ 2nd Generation Image Sensors QIS possible 3rd Generation Film Photography and vacuum tubes Early CCD and CMOS Research and Development CCD Commercialization CMOS Re- emergence Quanta Image Sensor Research and Development

5. Charge Coupled Device 11/29/2016 11:39 PM 5 By Michael Schmid - animated drawing created myself, CC BY 2.5,https://commons.wikimedia.org/w/index.php?curid=347838 • MOS-based CCDs are just like shift registers • CCDs were the first solid state detectors CCD Architecture has three basic functions: a) Charge Collection b) Charge transfer c) The conversion of charge into a measurable voltage Fig. 4 Full-frame CCD array architecture

6. CMOS Image Sensor (CIS) 611/29/2016 11:39 PM Fig. 5 CMOS image sensor (CIS) Floorplan Source: M. Bigas, E. Cabruja, J. Forest, and J. Salvi, “Review of CMOS image sensors.” Microelectronics Journal, 37(5):433-451, 2006 •“Achilles’ Heel” of CCD technology – The need for perfect charge transfer •Low power consumption •High integration capability •System-on-chip: miniaturization •Cost-effective

7. Active Pixel Sensor (APS) 711/29/2016 11:39 PM • Active amplifier within a pixel • 3T PD APS and 4T PD APS • Transversal signal line (TSL) • Overcomes SNR issue of PPS • kTC noise exists • Photodetection and photoconversion regions are same Fig. 7 A 3T Photodiode type Active Pixel Sensor schematic Source: M. Bigas, E. Cabruja, J. Forest, and J. Salvi, “Review of CMOS image sensors.” Microelectronics Journal, 37(5):433-451, 2006 Eric R. Fossum Fig. 6 Active Pixel Sensor

8. Comparison Between Pixel Architecture PPS 3T-APS 4T-APS(PD) 4T-APS(PG) Log Sensitivity Depends on the performance of a charge amp Good Good Fairly Good Good but poor at low light level Area consumption Excellent Good Fairly Good Fairly Good Poor Noise Fairly good Fairly good (no kTC reduction) Excellent Excellent Poor Dark Current Good Good Excellent Good Fairly good Image LAG Fairly good Good Fairly good Fairly good Poor Process Standard Standard Special Special Standard Note Very few commercialized Widely commercialized Widely Commercialized Very few Commercialized Recently Commercialized 11/29/2016 11:39 PM 8 Source: Jun Ohta, “Smart CMOS Inage Sensors and Applications,” CRC, 2008

9. Pinned Photodiode • Addition of shallow p+ layer • Fixed VPIN voltage based on doping concentration • High quantum efficiency • Low dark current • Lower pixel noise • Low light imaging • Widely used in industry 11/29/2016 11:39 PM 9 Fig. 8 Cross section of pinned photodiode Fig. 10 FSI PPD Potential well diagram Fig. 9 BSI CMOS PPD

10. Geiger Mode APD 11/29/2016 11:39 PM 10 Fig. 13 APD in standard CMOS technology Source: Jun Ohta, “Smart CMOS Image Sensors and Applications”, CRC 2008 • Single photon avalanche diode (SPAD) • Ultra low light detection Fig. 11 Transistor level diagram of pixel Fig. 12 I-V characteristics of SPAD

11. Comparison of CCD and CMOS Sensors 11/29/2016 11:39 PM 11 • CCD advantages over CMOS are the sensors’ higher quantum efficiency (QE) and generally lower noise • A strong advantage for CMOS technology is that it provides digital output and can be controlled at the pixel level • CMOS Camera-on-a-chip technology is better than CCDs because: – Much lower power - important for portable applications – System-on-a-chip integration allows smaller cameras – Lower cost of sensor chip and fewer components in camera – Easy digital interface for faster camera design & time to market – Less image artifacts - no blooming or smear, with same sensitivity – Higher dynamic range for security and auto applications – Digital output for faster readout speeds and frame rates – Direct addressing of pixels allows electronic pan/tilt/zoom – Faster design cycles means faster evolution path

12. Recent Technologies and Development • Dual Pixel Sensors • EOS 70D: Dual Pixel CMOS AF • Dual Sensitivity Pixel Technology 1211/29/2016 11:39 PM Source: www.imaging-resource.com

13. Deep Trench Isolation • In 2015, Deep Trench Isolation in Iphone 6s and 6s plus for low light image capture • Hold electrons and avoid leakage from pixel 11/29/2016 11:39 PM 13

14. QuantumFilm by InVisage 11/29/2016 11:39 PM 14 • QuantumFilm has a natural light response curve matching the human eye • High absorption capacity increases High Dynamic Range • Thin layer, less crosstalk

15. Quanta Image Sensors • Quanta Image Sensor concept was conceived in 2004 • Aim: Shrink pixel size • “Count every photon that strikes the sensor” – E. Fossum • Specialized photoelement: “Jot” (Greek for “smallest thing”) • Sub-diffraction limit (SDL) pixels – Digital Camera Sensors • Compatibility with a CMOS fabrication line 11/29/2016 11:39 PM 15

16. Creating Image from Jots 11/29/2016 11:39 PM 16 • Jots readout at 1000 fps resulting series of bit planes • This bit data results in the Jot data cube as shown in Fig 16 • Image can be created from the sum of a small x-y-t “cubicle” • The cubicle determine the spatial and temporal resolution of the output imageFig. 17 Concept to obtain image from jots. From [3]

17. Jot Devices • Pump-gate jot and bipolar-based jot 11/29/2016 11:39 PM 17 Fig. 18 (a) Pump-gate jot schematic (b) TCAD simulation (c) Bipolar-based jot TCAD simulation. From [4] (c)

18. Single Bit QIS Vs Multi-bit QIS Single Bit Multi-bit • Each jot produces 1 bit • Each jot produces n bits • 1 bit ADC • n-bit ADC • For same flux capacity, need higher frame rate readout • For same flux capacity, lower relative frame rate 1/2 (

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