Published on September 19, 2007
C3 and Wii Philosophy -IC Manufacturing Partnership Enabler Dr. Chyi S. Chern Manufacturing Technology Center , TSMC
Outline C3 in the IC industry Competitiveness Cost Effectiveness Collaboration and Co-development Wii (Win-Win) in the Supply Chain Not only Disintegration but also integration Customer Needs vs Productization Strategy Profitable and Healthy Supply Chain A new Integrated Partnership Model Summary
C3 Philosophy Competitiveness Advanced Technology Productization and Manufacturing Excellence Customer Partnership Cost Effectiveness Collaboration and Co-development
Moore’s Law and More Source: 2005 ITRS Moore’s Law: the downscaling of minimum dimension enable the integration of an increasing number of transistors on a chip The integration of CMOS- and non-CMOS technology within a package will become increasingly important.
Rapid Advancement of CMOS Cu/LK3.0 Lg= 115nm ′00 ITRS Technology Generation (nm) 130 ′01 ITRS 90 65 ′05 ITRS TSMC 45 Cu/ELK2.5 ′06 ITRS Lg= 30nm 32 Cu/XLK2.0 22 Lg= 13nm ‘00 ‘02 ‘04 ‘06 ‘08 ‘10 ‘12 ‘14 ‘16 ITRS: International Technology Roadmap for Semiconductors Technology leadership is essential to meet cost, power, performance, quality and time-to-market requirements of customers
Accelerated Yield Learning for Technology Generations 65nm 90nm 0.13μm D0 (Arb. Units) 0.18μm 0.25μm 03 04 06 00 01 02 05 07 20 20 20 20 20 20 20 20
Broadening Beyond CMOS Logic TSMC Technology Offerings 32nm 45nm 65nm 90nm 0.13μm 0.15/0.18μm 0.25μm 0.35μm >0.5μm Specialty Embedded Embedded Logic Mixed High CMOS Image Memory Flash DRAM Signal/RF Voltage Sensor Available Now Development
Typical Production Ramp-up Source: 2005 ITRS Production tools typically need 12 to 24 months to develop prior to ship to customers. Product qualification may take 12 to 24 months to reduce D0 to meet volume production scale.
Quick Delivery of Technology Solution through New Tool Design (AMAT) Challenge of STI gap filling Quick solution Vertical profile, Complete Fill HARP IE No void/ No seam +
Fast Development of Advanced Tool Roadmap Standing alone tools All-in-one solution Clean + WN glue + W plug + SiCoNi ALD W ALD WN ALR CVD W PNL WN 50% CoO Reduction RPC WCVD 50% Rc Reduction Ti/TiN Glue
Albany NanoTech Center (ANT) Albany NanoTech (ANT) Albany NanoTech is a fully-integrated research, development, prototyping, pilot manufacturing and education resource managing a strategic portfolio of state-of-the-art laboratories, a supercomputer and shared-user facilities and an array of research centers located at the University at Albany - SUNY. The Albany NanoTech complex boasts the only fully integrated 200mm/300mm wafer resource of its kind in the world for prototyping and integration of nanotechnology innovations. Its portfolio of programmatic activity ranges from emerging computer chips with higher functionality and complexity, to nanosystems based sensor- and system-on-a-chip technologies. Albany NanoTech works with over 100 companies located worldwide providing technology development and commercialization support for pre-competitive and proprietary projects. ANT - Sematech North The establishment of Sematech North at Albany NanoTech is the first expansion of Sematech beyond its Austin, Texas headquarters and research facility since the consortium was founded in 1987. A joint five-year $320M program is in place to conduct research and development in the area of advanced lithography infrastructure for extreme ultraviolet (EUV) lithography. ANT - Tokyo Electron Technology Center America Tokyo Electron Limited’s (TEL) Albany R&D facility complements and expands its global research and development activities, as well as manufacturing capabilities in Austin, Texas; Phoenix, Arizona; and Boston, Massachusetts. It is the first research center to be located outside of Japan. In Albany, TEL performs advanced tool design and prototyping and access to the facilities has enhanced internal development efforts shortening the time required to bring critical technology from the research lab to the production floor. ANT - Center of Excellence in Nanoelectronics The Center of Excellence in Nanoelectronics at Albany NanoTech is a fully-integrated technology deployment, product prototyping, manufacturing support, and workforce training resource for emerging generations of integrated circuitry (IC). Its targeted portfolio of nanoelectronics-based products ranges from emerging microprocessor and memory computer chips with higher functionality and complexity, to the rapidly evolving areas of micro- and nanosystem based quot;systems-on-a-chipquot; (SOC) technologies, including biochips, optoelectronics and photonics devices, and nanosensors for energy and the environment. ANT - Center for Advanced Thin Film Technology This university/industry/State initiative has two objectives: to advance the productivity, competitiveness and expansion of existing industries in critical thin film and coating areas of key relevance to advanced electronics, optoelectronics and photonics and to support the creation, spin-off and growth of new industries in these areas. The Center for Advanced Thin Film Technology offers an array of unique resources for thin film processing, patterning, characterization and analysis. Primary areas of research include microelectronics, optoelectronics/photonics, hard coatings and advanced energy technologies. Research programs include computer chip interconnects, vapor phase processing, characterization and modification of materials, materials and plasma, electron microscope studies of materials, ion beam characterization, and modifications of materials and x-ray and neutron optics. Resources include state-of-the-art 8-inch wafer computer fabrication, patterning and testing facilities; cluster tools for no-exposure-wafer processing and etching; high-resolution atomic imaging systems; and a complete array of ion beam, electronic beam, and x-ray diagnostic and failure analysis equipment.
Intimate Customer Partnership • Seamless collaboration with customers for realization of optimal product performance and the shortest success learning curve • Competent FA engineering capability of devices, circuit layout, IC process , assembly, and testing Wafer Design Service Manufacturing Product Engineering CP Test Customer Production window analysis Design Device/circuit simulation Packaging Statistical analysis Electrical FA Final Test Physical FA
C3 Philosophy Competitiveness Cost Effectiveness Innovative Cost Reduction Methodology Innovation Productivity Breakthrough Innovative Capacity Planning and Allocation Collaboration and Co-development
Increasing Fab cost by Technology nodes Source: Garner 07
Steep Price Erosion of Consumer Electronics 100 80 ASP (Arbitrary Unit) Digital Camera Digital TV DVD Players 60 40 20 0 1998 2000 2002 2004 2006 2008 Year Source: iSuppli, tsmc, 2005
Innovative Cost Reduction Methodology Electrolyzed Sulfuric Acid Cell Reuse H2SO4 + H2O → H2SO5 + 2H+ + 2e- Sulfuric Distillation Acid Recycle Particles filtration Cost Metal removal Reduction Reclamation Gypsum Fertilizer Cement
Tool analysis: tool Productivity Simulator Complex & Powerful Simulator Wet CEE Log Analyzer WISDOM Development new methodology for tool productivity improvement The Tool Internal Motion is not Black Box any more Simple & Faster Tool Optimization Tool Enhancement •Benchmarking •New mechanism •Chamber idle •New control logic
Productivity Breakthrough through DFM • Producer GT: – Original Design can’t meet Foundry’s complex high-mix operation, DFM tool can improve near 30% idle time. Original Best for Producer GT Producer SE Production 3rd Chamber Dual Blade Dual LL 4 LPs 30% WPH 90% WPH improvement improvement COO reduce 20%
Fab Scale and Flexibility • Scale and flexibility accommodate the impact of high product Mega mix Mini Regular fab fab fab Mini Regular Mega Cycle Time Mini fab fab fab Scale (WSPM) ~10K ~25K ~80K fab Scale (WSPM) 1~10K ~25K ~80K CAPEX ($B) 3~4 6 Mega CAPEX ($B) 1 3~4 6 fab Tool Backup Limited Medium Flexible Tool Backup Limited Medium Flexible Fab Utilization Product Ramp Limited Medium Agile Product Ramp Limited Medium Agile Mini Operating High Medium Low fab Cycle Time CostOperating Cost High Medium Low Infrastructure Limited Medium Vast Infrastructure Limited Medium Vast Mega Cycle Time Long Medium Short fab Cycle Time Long Medium Short Delivery Unstable Medium Precise Time Delivery Unstable Medium Precise
C3 Philosophy Competitiveness Cost Effectiveness Collaboration and Co-development Flexible Collaboration with Research Institutes DFM’s in the Supply Chain Integrated Partnership
Flexible Collaboration with Research Institutes tsmc ITRI BEOL FEOL MRAM Co-development Low cost Fast read/write speed CMOS compatible
Collaborative Service Partnership Reactive and local optimization Proactive and global optimization Design for Manufacturing Market Design EDA Lib/IP Foundry Backend Point Tool Yield Basic Solution Building Improvement Blocks Design for Test
DFM Ecosystem Total Solutions Customers Virtual Platform DFM Compliant DFM Compliant DFM Data DFM EDA Tools IP/Library & Utilities Services IP/Lib Alliance TSMC (Foundry) IP/Lib Alliance DFM Partners DFM Partners EDA Alliance EDA Alliance DFM Partners DFM Partners
Accurate Technology Modeling Silicon Modeling- Within Die Variation As Manufactured Scaling results in tightening of circuit timing requirements Timing variability reduction is key issue OPC, CMP, (R,C), dummy insertion models, verified on circuits and integrated into EDA tools
Technology Model Application - CMP Cu thickness variation reduction during design Design Layout CMP Simulation CMP Cu Thickness & “Hot Spot” Display CMP Hot Spot Fix CMP Simulation CMP Cu Thickness & Hot Spot Display
Technology Partnership with Tool Supplier ECP defect eliminated by partnership with tool supplier. Defect-free Yield Killing Process Defect Tool Supplier Substrate Hardware Control Design Failure Analysis, Integration Failure Mechanism Optimization Foundry
Technology Partnership with Material Supplier Cu sheet resistance uniformity improved by partnership with material supplier Chemical supplier (arb. Unit) Optimization of 2.0 Chemistry and abrasives 1.5 1.0 Integration Issues and optimization spec. definition Foundry
Customized Interconnect Offerings TSMC offers customized interconnect to meets the needs of high packing density, high performance (low-K, low-R), and low cost. Example 45nm BEOL High Performance Standard Cell e.g. MPU e.g. ASIC, GPU,… Mz 2XMetal Mz Mz USG, k=4.2 10 Min/Max metal layers: 1-2 Mz My Mz 9 Low-k, k=2.9 Min/Max metal layers: 1-2 My Mx 8 My Mx Mx 7 Low-k , k~2.55 Mx Mx 6 Min/Max metal layers: Mx > 1-7 for standard cell Mx 5 > 1-5 for high performance Mx Mx 4 Mx Mx 3 Mx M1 Mx 2 Low-k, k~2.55 M1 1 M1 Min/Max metal layers: 1
3-Way Integrated Technology Partnerships ELK (2nd generation low-k) realization through the joint efforts of material and tool suppliers. Tool Supplier ELK ELK Realization Requirement PECVD E-Beam deposition UV Curing Foundry Integration Optimization Pore Porogen Inorganic matrix Control of ELK Successful material and ELK integration Material Supplier mechanical strength
Wii (Win-Win) Philosophy Not only Disintegration but also integration Vertical integration vs Horizontal disintegration Supply chain transformation behavior Business Position control through Standardization Customer Needs vs Productization Strategy Profitable and Healthy Supply Chain
Supply Chain Integration or Disintegration - Bi-helix model by Prof. Charles Fine/MIT standpoint Vertical Horizontal Integration Industry Disintegration Industry Integrated product Modulated product Competitors with Technology unique technology Breakthrough Multi-domain know- Supplier dominates how complexity the market Look for Look for High profit resulted Organizational Horizontal vertical from proprietary Rigidity Disintegration integration system
Example of Supply Chain Transformation Behavior - PC Industry (1/2) • Vertical Integrated Computer Industry and integrated product offering – 1975 ~ 1985 IBM DEC Others CPU OS Peripheral Application Software Network Services HW Integration
Example of Supply Chain Transformation Behavior - PC Industry (2/2) • Horizontal Divided Computer industry and modularized product offering – 1985 ~ 1995. Intel Moto AMD Others CPU MS Mac Linux OS Peripheral HPQ EPSON Seagate Others Application Software MS Lotus SAP CA HW Integration Dell HPQ IBM Others
The Disintegration of Semiconductor Industry IDM/ASIC System Co. IDM/ASIC IDM/ASIC Fabless Co. Fabless Co. System System Design System Design Design System System IP Design IC IC Design IC Design IC Design Design Design IC Design System/IC Design Design Services Fab Fab Fab Foundry Foundry Assembly & Test Assembly Contract & Test Assembly Assembly & Test Assembly & Test & Test 1986 年以前 1990 年代 2000 年以後
Number of equipment companies (generating 80% of total WFE avenue) Possibilities to provide acceptable ROI for equipment company Equipment company process development alliances and mergers. Create joint technology development consortia between semiconductor manufactures and equipment manufactures.
Wii (Win-Win) Philosophy Not only Disintegration but also integration Customer Needs vs Productization Strategy “Design-in” for Tools, Silicon Processing, and IP’s Products serves as Exact solutions to Customers or Customers’ profitability Products serves as Best Tools to Customers or Customers’ profitability Profitable and Healthy Supply Chain
The IC Industry Driver in each Decade 10 Unit/end user 1 Consumer Electronics PC 1/10 Minicomputer 1/100 Mainframe 1970 1980 1990 2000 2010 Year
Digital Convergence and Ubiquitous Environment - Create new phases of needs
Apple Digital Music Domain Trilogy - integrated innovative service model Source: STPI 05 Apple company provides Music everywhere service through package of iPod + iTunes + peripheral products to meet consumer needs with enormous value than individual innovation.
Technology Portfolio Required by Broad-based Consumer ICs High Growth High Volume • Digital TV/Set-top Box • Cellular Base-Band Technologies • Cellular Application • Graphic Processor Advanced Processor • Hard Disk Drive • Game Console • High End Switch & Router • Wireless LAN • High End Printer • High Speed SRAM • TFT-LCD Controller/Driver • Sensor Regulator Interface Technologies Mainstream • CMOS Image Sensor • MCU with Embedded Flash • RFID • Power Management • PC Peripheral Advanced Tech.: <0.15μm Advanced Tech.: <0.1Advanced Tech.: <0.15μm Source: tsmc Mainstream Tech.: ≥0.15μm Mainstream Tech.: ≥0.15μmMainstream Tech.: ≥0.15μm
Accelerated Delivery of Advanced Technologies for SOC Applications (TSMC) More varieties More integrated Shorter time-to-market CLN90G CLN45GS CLN65GP General Purpose General Purpose CLN45LPG CLN65LPG Low Power Low Power CLN90LP CLN65LP CLN45LP CLN65HS High Speed CLN45SOI High Speed CLN90GT CLN65SOI CMN90LP CMN45LP CMN65LP MS/RF CMOS MS/RF CMOS CRN65LP CMR45LP CRN90LP CLN65G CLN45GS Emb HDMTM Emb HDMTM CLN90G CLN65LP CLN45LP CLN90LP 2003 2004 2005 2006 2007 2008 * Left edge of each box represents initial production schedule.
Wii (Win-Win) Philosophy Not only Disintegration but also integration Customer Needs vs Productization Strategy Profitable and Healthy Supply Chain Minimized Development Endeavor/Cost Best Timing to the Market and Volume Solid Partnership with key Customers and Suppliers
Increasing R&D and Capital Investment Required to Meet Growth Challenges 16 6 14 Fab Costs R&D Cost Relative to 0.25 R&D Costs 5 12 4 Cost US$B 10 3 8 6 2 4 1 2 0 0 90nm 65nm 45nm 32nm 0.25 0.18 0.13 N90 N65 N45 N32 Technology Node Technology Node Costs are now prohibitive for many companies to continue to invest
Collaborative R&D with TSMC Customer TSMC Supplier Past Phase - in Tech. Dev. Tech. Dev. JDP with Research Now Customer & Industry / Uni. Supplier Goal: Aggressive foundry baseline with flexibility to meet each customers’ requirements for cost, power, performance, quality
Shortening Time-to-Volume of Consumer Electronics Color B&W Mobile DVD VCR TV TV phone 1M Units Sales Volume 0 2 4 6 8 10 12 14 16 18 20 Years after Introduction Source: Semico Research
Participants in the Semiconductor Industry Value Chain Profitable supply chain needs the ability to add value on a cost advantage, on differentiation. The structure changes periodically, depending on the degree of vertical integration that maximizes profits in time.
A new Integrated Partnership Model
Factory Integration Scope
A New Integrated Foundry Model
Integrated Foundry Model Concurrent, Proactive & Global Optimization Customer Product Design Design Infrastructure Design IP Product Requirement Technology Definition Models and Foundation Models and Design Foundry Tech. IP Flow Development EDA Lib / IP Product System Specification Package Models Package Models Backend Package Models
Advantages of the New Integrated Relationship • Increased incorporation of customer requirements (cost, power, performance, quality) into foundry process technology • Access to foundry design environments to reduce design cycle time • Assurance of wafer capacity and manufacturing ramp- up goals • Vertically–integrated technology availability (design, wafer production, assembly, test) for faster time–to– market
Summary C3, Competitiveness, Cost effectiveness and Collaborative co-development are addressed as the keys to enable partnerships in IC manufacturing industry. The disintegration and somewhat integration business model should both co-operate to achieve win-win in the IC manufacturing supply chain. Integrated partnership will result in minimized development effort and cost, successful products and good services, and helpful to give best timing to the market as well as to the required volume.
TSMC OIP: What to Do With 20,000 Wafers Per Day. Paul McLellan 09-17-2015. ... TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC. by . Paul McLellan.
Tools Tools for: System Design and Verification; Functional Verification; Logic Design
WILSONVILLE, Ore., Apr. 26, 2005 - Mentor Graphics Corporation (NASDAQ: MENT) today announced that Walden C. Rhines, the company's chairman and CEO, will ...
Programs include CEO Forum, IC Packaging Summit, Keynotes and MEMS Forum
TSMC Technical Symposium Will Highlight Technology Roadmap for Semiconductor Foundry; Lester Thurow to Provide Keynote Address at Annual Event
This will be my 30th DAC. I know this because my first DAC was the same year I got married and forgetting how many years your have been married can cost ...
TSMC keynoter touts cooperative business models. Dylan McGrath. ... (TSMC). Delivering a keynote address at the Design Automation Conference here Tuesday ...
TSMC Acting Spokesperson: Elizabeth Sun Senior Director, TSMC Corporate Communications Division TEL: 886-3-5682085 Email: firstname.lastname@example.org: Company ...