Sytem verilog golden reference guide

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Sytem verilog golden reference guide

System Veri log GOLDEN REFERENCE GUIDE A concise guide to SystemVerilog IEEE Std 1800™-2005 /�DOULOS

SystemVerilog Golden Reference Guide Version 4.0, January 2006 Copyrlghl@1995-2006 by Doulos Ltd. All Rights Reserved The information contained herein is the property of Doulos Ltd and is supplied without liability lor errors or omissions. No part may be used. stored, transmitled or reproduced in any form or medium without the writlen permission or Doulos ltd. Doulos"' is a registered trademark of Doulos ltd. 1800r"' is a trademark and IEEE" is a registered lrademark. Verilog-XLTM is a trademark and Verilog" a registered trademark of Cadence Design Systems Inc. All other trademarks are acknowledged as the property of their respective holders. First published by Doulos Ltd 2006 ISBN 0-9547345-3-X Doulos ltd. Church Hatch 22 Market Place Ringwood Hampshire BH241AW UK Tel +44 (0)1425 471223 Fax +44 (0)1425 471573 Email: Web: htlp://

Contents Page Preface ............................ ....................................................................... Using This Guide .................................. ...... . .... ..................................... A Brief Introduction To SystemVerilog Syntax Summary ................................................................................. Alphabetical Reference Compiler Directives ...................................................................... .......................................................................... 6 8 16 31 339 ......................................................... 353 .......................................................................... . ....................... 395 System Tasks And Functions Index .............................................. 5

Preface The SystemVerilog Golden Reference Guide is a compact quick reference guide to the SystemVerilog language as defined in the IEEE Standard Verilog Language Reference Manual, IEEE Sid 1 364-2005 and IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language, IEEE Sid 1800-2005. The intention of the guide is to provide a handy reference. It does not offer a complete, formal description of SystemVerilog. Rather, it offers answers to the questions most often asked during the practical application of SystemVerilog, in a convenient and concise reference format. It is hoped that this guide will help you understand and use SystemVerilog more effectively. This guide is not intended as a substitute for a full training course. and will probably be of most use to those who have received some training. The SystemVerilog Golden Reference Guide was developed to add value to the Doulos range of Training courses, and to embody the knowledge gained through Doulos methodology and consulting activities. For more information about these. please visit the web-site You will find a set of SystemVerilog tutorials at CopyooghlC 11195-2006 by Doulo• Lid 5

Using This Guide The SystemVerilog Golden Reference Guide comprises a Brief Introduction to SystemVerilog, a Syntax Summary, the Alphabetical Reference sections and an Index. If you are new to SystemVerilog, you should start by reading A Brief Introduction to SystemVerilog, which follows. The major new areas of SystemVerilog are introduced and explained in more detail in a number of tutorials, which you will find at Data types RTL design • Interfaces • Assertion-based verification • Testbench automation and constraints • The Direct Programming Interface (DPI) Clocking Classes The main body of this guide is divided into three parts: SystemVerilog Alphabetical Reference, Compiler Directives and System Tasks and Functions. Each of these is organised alphabetically into sections and each section is indexed by a key term, which appears prominently at the top of each page. Often you can find the information you want by flicking through the guide looking for the appropriate key term. If that fails, there is a full index at the back. New In SystemVerllog This guide covers the full SystemVerilog language, which is based on Verilog2005. In each section in the main alphabetical reference, the main changes introduced in SystemVerilog are highlighted using the following notation. � This feature was added in SystemVerilog Where there is no such indication, the feature is the same as in Verilog-2005. You will find information about the differences between Verilog-2001 and Verilog-2005, and between the different versions of SystemVerilog in the article SystemVerilog Versions. The Index Bold index entries have corresponding pages in the main body of the guide. The remaining index entries are followed by a list of appropriate page references. 6 Cop)'ighl 0 1995·2006 by Doolos Lid.

Key To Notation Used To Define SystemVerllo Syntax g The syntax definitions are written to look like examples wherever possible, but it has been necessary to introduce some extra notation. In brief, square brackets [] enclose optional items, three dots ... means repetition, and curly brackets 0 enclose comments. ltalicNames represent parts of the syntax defined elsewhere. A full description of the notation follows: Curly brackets {} enclose comments that are not part of the SystemVerilog syntax being defined, but give you further information about the syntax definition. Bold curly brackets {} are part of the SystemVerilog syntax (e.g. the concatenation operator). Syntax enclosed in square brackets [ ] is optional. Bold square b rackets ( ) are part of the SystemVerilog syntax (e.g. vector range). . .. means zero or more repetitions of the preceding item or line, or means a list, as follows: Item ... means zero or more repetitions of the Item. , ... means repeat in a comma separated list (e.g. A, B, C) ; .. . means repeat in a semicolon separated list. Words in lower-case letters are SystemVerilog keywords (e.g. module). Capitalised Words (not in italics) are SystemVerilog identifiers, i.e. user defined names that are not keywords (e.g. lnstanceName). Italic Words are syntactic categories, i.e. the name of a syntax definition given in full elsewhere. A syntactic category can be either defined on the same page, defined on a separate page, or one of the special categories defined below. Italics = indicates a syntactic category which is defined and used on the same page. In each article in the alphabetical reference section, the heading "Where" immediately follows the "Syntax" heading. This tells you where the construct can be used. For example. $unit module-<HERE>-endmodule i n terface-<H ERE>-end in terface means that the construct being described can be in the compilation unit (i.e. outside any modules etc. -see the articles Name and Compilation Unit), in modules and interfaces, but not in programs, for example. Copyright C 1995·2006 by Doulos Ltd. 7

A Brief Introduction To System Veri log The following paragraphs give a brief technical introduction to SystemVerilog suitable for the reader with no prior knowledge of the language. What Is SystamVarllo ? g SystemVerilog (IEEE Std. 1 800-2005) is set of extensions to the Verilog Hardware Description Language (IEEE Std. 1 364-2005). SystemVerilog is used to simulate and verify the functionality of digital electronic circuits at levels of abstraction ranging from system level, stochastic and pure behaviour down to gate and switch level, and is also used to synthesize (i.e. automatically generate) gate level descriptions from more abstract (Register Transfer Level) descriptions. SystemVerilog is commonly used to support the high level design (or language-based design) process, in which an electronic design is verified by means of thorough simulation at a high level of abstraction before proceeding to detailed design using automatic synthesis tools. SystemVerilog is also widely used for gate level verification of ICs, including simulation, fault simulation and timing verification. g A Brief Histo of Verllo and S stemVerilo ry y g The Verilog HDL was originally developed together with the Verilog-XL simulator by Gateway Design Automation, and introduced in 1 984. In 1989 Cadence Design Systems acquired Gateway, and with it the rights to the Verilog language and the Verilog-XL simulator. In 1990 Cadence placed the Verilog language (but not Verilog-XL) into the public domain. A not-for-profit organisation, Open Verilog International (OVI) was formed with the task of taking the language through the IEEE standardisation procedure, and Verilog became an IEEE standard in 1 995. In 2000, OVI combined with VHDL International to form Accellera. In 2001 the ilog, generally known as Verilog-2001, IEEE released a revised version of Ver with the standard number IEEE Std. 1 364-2001. This version incorporated many useful improvements. In 2002 Accellera introduced extensions for a higher level of abstraction for modelling and verification with the Verilog HDL, under the name SystemVerilog 3.0. An extended version - SystemVerilog 3.1 - and a further revision - SystemVerilog 3.1 a - were introduced in 2003 and 2004 respectively. SystemVerilog 3.1 a formed the basis for the IEEE standardisation of SystemVerilog, resulting in IEEE Sid 1800-2005, which is the subject of this guide. At the same time, Verilog itself was revised to resolve some incompatibilities and inconsistencies with SystemVerilog. This revision of Verilog is IEEE Sid 1 364-2005. 8 Copynght C 1995-2006 by Doulos Ltd

A Brief Introduction to SystemVerllog g Sources of SystemVerllo The SystemVerilog extensions come from a number of sources: A subset of the proprietary Superlog language, which was donated by Co-Design Automation (now part of Synopsys); Veralite (testbench) and the DirectC, assertions and coverage APis, which were all donated by Synopsys; Accellera PSL 1 .0 assertions (which were in turn derived from IBM's Sugar language); and proposals from the Accellera SystemVerilog committee. g g Summa of SystemVerilo Extensions to Verilo ry SystemVerilog adds important new constructs to Verilog, including: New data types: byte, shortint. int, longint, bit, logic, string, chandle. Typedef, struct, union, tagged union, enum Dynamic and associative arrays; queues Classes Automatic/static specification on a per variable instance basis Packages and support for Compilation Units Extensions to Always blocks for modelling combinational, clocked processes • latched or Jump Statements (return, break and continue) Extensions to fork-join disable and wait to support dynamic processes. , Interfaces to encapsulate communication Clocking blocks to support cycle-based methodologies Program blocks for describing tests Randomization and constraints for random and directed-random verification • Procedural and concurrent assertions and Coverage for verification Enhancements to events and new Mailbox and Semaphore built-in classes for inter-process communication. The Direct Programming Interface, which allows C functions to be called directly from SystemVerilog (and vice versa) without using the PLI. • Assertions and Coverage Application Programming Interfaces (APis) and extensions to the Verilog Procedural Interface (VPI) - details of these are outside the scope of the SystemVerilog Golden Reference Guide Cq>yright C> 1995-2006 by Dootos Ltd 9

A Brief Introduction to SystemVerilog The Language In this section as in the rest of the guide, words given in Capitalised Italics are technical terms whose definitions may be found in the main body of this guide. Source Files SystemVerilog source code is written in one or more text files. These files are grouped into Compilation Units in a tool-specific way. The default is that each file is a separate compilation unit. The source text includes the declaration and use of Modules, Programs, User­ Defined Primitives, Interfaces and Packages, as well as Compilation Unit declarations outside any named Modules etc. Comments may be started with//, ending at the end of the line, or block comments I" ... *I may be used. Hierarchy A hierarchical portion of a hardware design is described in SystemVerilog by a Module. The Module defines both the interface to the block of hardware (i.e. the inputs and outputs) and its internal structure or behaviour. module M (inp ul A, B, Clk, output r); II Functional description goes here endmodule The communication between blocks may be encapsulated in Interfaces. Interfaces allow design refinement from system-level down to RTL and structural levels, totally independent from modules. A number of primitives, or Gates, are built into the SystemVerilog language. They represent basic logic gates (e.g. and, or). In addition User Defined Primitives (UDPs) may be defined. Programs are used to describe simulation tests. Programs are instanced in modules (typically in the top-level testbench), but are themselves leaves in the hierarchy. Like modules, programs may have ports. The structure of an electronic circuit can be described by making Instances of Modules and Primitives (UDPs and Gales) within a higher level Module, and connecting the Instances together using Nets and Variables. These represent simple electrical connections, a wire or a bus. Communication between Modules can be encapsulated using Interfaces. At its simplest, an Interface is a bundle of Nets or Variables. Interfaces may also encapsulate functionality. A list of Port connections is used to connect Nets, Variables and Interface Instances to the Ports of a Module, Interface or Primitive Instance, where a Port represents a pin. 10 COf•jTight C 199�2000 by Doulos Lid.

A Brief Introduction to SystemVerllog module AOI ( i nput A, B, C, output r); wire W1, W2; and (1"11 , A, B ) ; assign F � II C); (W2, W1, or Instance of "and" gate II Instance of "or" gate II !W2; Continuous assignment endmodule Nets and Variables SystemVerilog has two classes of data type: Nets and Variables. Nets can be used to form connections and be the target of continuous assignments (Assign). They may have multiple drivers. Variables can also be used to form connections and be the target of continuous assignments. They can also be the target of Procedural Assignments in a process (Initial or Always). If a Variable is driven by a continuous assignment or by being connected to an output Port, it may not be driven or assigned values in any other way. However, a given variable may be assigned values from more than one process. Literal Values Integer literals may be specified using binary, octal, decimal or hexadecimal notation. The size (number of bits) and signing (signed or unsigned) may bo given. Underscores L) may be included to aid readability. SystemVerilog also includes real, lime, string, array and struct literals. 23 II A decimal integer (32 bits) -15 II A negative decimal number 8'bll10 0001 II B'so77 II An 8-bit unsigned binary number An 8-bit signed octal number 'hf[ 11 An unsized, unsigned hexadecimal number 16'bz II lx II lOns II Time literal I { 0 , 1, 21 II Array literal - assignment pattern II Struct literal - assignment pattern String literal (8 bits/char = 40 bits) 1 {0, "llcllo", 2.3) 11Hellon II Same as 16'bzzzz_zzzz_zzzz_zzzz Sets all bits to x Data Types SystemVerilog includes a number of integer data-types. These may be signed or unsigned. These are a hybrid of both Verilog and C data types, to provide for accurate translations to and from C. The 2-state (01 1 ) integer types are: bit, byte, shortint, inl, and longinl. The 4state (0, 1 , X, Z) integer types are: logic, reg, integer and time. Of these, bit, Cop)Tight 0 1 �S.2006 by Doutos Ltd 11

  • A Brief Introduction to SystemVerilog logic and reg have a user-defined size (number of bits). The others have a fixed size. Types logic and reg are identical; in SystemVerilog, logic is preferred. The non-integer Variable data types are shortreal, real and realtime. For a better encapsulation and compactness of code Structs, Unions and Enum types may be used. User defined types may be defined with Typedef. Both Nets and Variables may have data types. Multi-dimensional arrays of Nets and Variables may be defined. II Integers shortint s ; II byle un9igncd b ; 1 6-bit, 2-state, signed II bit [9: 0 ] blO; reg signed [ 7 : 0) r ; II 8-bit, 2-state, unsigned I I 1 O-bit, 2-state, unsigned I I 8-bit, 4-state, signed Arrays logic [3:0) i[l:lO); integer a [ O : I S ] ; II Array of 1 D 4-bit, 4-state II Array of 16 32-bit, 4-state I I Anonymous Struct s t rucl I bit [ 7 : 0 ) Opcode; b i t [ 2 3 : 0 ] Addres s ; Reg; I I Anonymous enum cnum { red, yellow, green} LighL; User-defined type typedef enum START, STOP, WAIT} StaLcType; SLa LeType S L a L e , NextState; II Classes To support object-oriented programs, Classes may be defined. A class has properties (i.e. data members) and methods (i.e. Function and Task members). A Class may be extended to form a new Class (single inheritance). A Class is in effect a user-defined data type. Classes may be instanced to create objects. To support directed-random verification, Class Variables may be declared Random. Classes may also include Constraints, which direct the generation of random values. 12 Copynght o 1ggs 2006 by 0oo1os Ltd

    A Brief Introduction to SystemVerilog Behaviour The behaviour of an electronic circuit is described using Initial and Always constructs and continuous assignments (Assign). Constructs such as Always_comb, Always_ff and Always_latch are used to describe design intent for synthesisable circuits. Along with UDPs and Gates these represent the leaves in the hierarchy tree of the design. Each Initial, Always, continuous assignment, UDP and Gale Instance executes concurrently with respect to all others, but the Statements inside an Initial or A/ways are in many ways similar to the statements in a software programming language. They are executed at times dictated by Timing Controls, such as delays, and (simulation) event controls. Statements execute in sequence in a Begin-End block, or in parallel in a Fork Join block. Fork-join blocks can be used to create new dynamic processes. A dynamic process executes in a separate parallel thread. Dynamic processes are particularly useful for pipeline modelling. Fine-grained control for Initial, Always and dynamic processes is provided by the built-in process class. ­ A continuous assignment modifies the values of Nels or Variables. An Initial or Always modifies the values of Variables. An Initial or Always can be decomposed into named Tasks and Functions, which can be given arguments. Tasks and Functions may be declared as Automatic or Static, with automatic and/or static variables that may be specified for each variable instance. Jump Statements enable jumping to the end of a loop, or exiting loops Functions or Tasks before completion. I I Continuous assignment assign Sum -A + B; Initial statement II iniLial forever H5ns Clock � -Clock; I I Combinational always always_comb begin Carry - a Sum = b; A a 1 b; end I I Clocked always always_ff @(posedge Clock iff Reset -- 0 if or posedge Reset) {Reset) Q <� 0; else Q <� Q I 1; Copyrighl 0 1995-2006 by Doulos Lid. 13
  • A Brief Introduction to SystemVerllog Interfaces Interfaces are a major new construct in SystemVerilog, created specifically to encapsulate the communication between blocks, allowing a smooth refinement from abstract system-level through successive steps down to lower RTL and structural levels of the design. Interfaces also facilitate design re-use. Interfaces are hierarchical structures that can contain other interfaces. Interfaces may contain Modports. These provide access and directionality for the interface members. Broadcast communication is modelled by extern forkjoin tasks in interfaces, which can be defined in multiple modules and executed concurrently. Assertions and Coverage An immediate assertion is used to test the value of an expression. Immediate assertions are procedural Statements. Prope rties are used to specify aspects of the design's behaviour. Properties may be built from one or more Sequences. Typically Sequences and Properties describe behaviour over time ("temporal behaviour") with respect to a clock. Properties may be checked using Concurrent Assertions. If an asserted property does not hold, the assertion is violated and an error is generated. Assertions may be checked dynamically during simulation, or statically using a property checker, which is a type of formal verification tool. Assertions may also be used to control test bench automation tools. Assume statements act like concurrent assertions during simulation, but property checkers assume they hold. Properties may be used in Cover statements. During simulation, these monitor evaluation of the property, and afterwards a coverage report is created. An Expect statement is a procedural statement that awaits and checks a specified Property. Expect statements are used in testbenches. 1 1 Immediate assertion AEQB : asserL (A •• Bl Sdlsp l ay ( "OK . A equ a ls B . " ) ; e l s e S error (" O h dear! A should equal B . . . " ) ; I I Property property A_lmplies_B_thcn_C ; @ (poscdge Clock) A 1-> B ##1 C; endproperty 11 Concurrent assertions rulel: assert properLy (A_impl ies_D_ then_Cl e l s e Serror ("a , b, c ouL o f sequence " ) ; prop! : cover property (A_ implies_B_ Lhen_C ) ; In addition to property coverage, SystemVerilog includes Covergroups for specifying functional coverage metrics. A Covergroup contains one or more 14 Cop)"n!ll11 0 1995- 2006 by Doolos lid
  • A Brief Introduction to SystemVerilog Coverpoints, which are Variables or Expressions for which functional coverage information is collected. Packages Declarations of Data Types, Classes, Functions, Tasks, Properties and Sequences may be made in Packages and Imported into Modules, Interfaces etc. This provides a means to share common declarations. Built-In Methods, System Tasks and Functions, the DPI and the PLI A number of methods are buill in to the language. For example Array Manipulation methods, Enum methods and String methods. There are also a number of built-in System Tasks and Functions. These cover a range of tasks, including reading and writing from files, stopping simulation, type conversions and stochastic modelling. inilial be g i n $display("Starting simulation ... "); $stop; end There is a built-in package, Std. which contains a number of system types. The Direct Programming Interface (DP/) allows functions in a foreign language (usually C) to be called as SystemVerilog functions. These are known as Imported functions. Conversely, a SystemVerilog function or task may be Exported. and called from tho foreign language. The Programming Language Interface (PL/) is an integral part of the SystemVerilog language, and provides a means of calling functions written in C in the same way as System Tasks and Functions. Com ilation p SystemVerilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a SystemVerilog compiler or interpreter, which builds the data files necessary for simulation or synthesis. Sometimes simulation immediately follows compilation with no intermediate data files being created. Two interlinked mechanisms, L brary and Configuration, accommodate library­ i based tools. The existence of libraries supports separate compilation of modules and allows different versions of a module to be used in different places in the simulation. Copyright C> 1935-2006 by Doutos Ltd 15
  • Syntax Summary Comp ilation Unit Compilation units contain interfaces, modules, programs and packages as well as declarations that are outside any of these and bind directives. Llmeuni L 1 OOns ; timeprecision lps; I I Compilation unit declarations - same as in a package I I Modules, Interfaces, Programs, Packages module . . . endmodulc interface ... endinterlacc program endp rogram package . . . cndpackage I I Bindings b i n d M Prog TestProg ( . . . ) ; bind M I n t Bus ( . . . ) ; bind M ml , m2 Mon i l o r ( . . . ) ; Packa e g package P; II Anonymous program program; I I Task, Function, Class, Covergroup declarations endprogram II Net, Variable, Type, Import, Virtual, Task, Function, DPI, Class, I I Parameter, Covergroup, Overload, Property, Sequence Declarations endpackage 16 p Cq>ynghtO t99S.2006 by Ooulos llo
  • Syntax Summary Module module Ml # (parameter N - 8) ( i nterface I n t , lnput logic P l , P 2 , outpul r e g [ 7 : 0 1 P3, i nout bit P� ) ; timeunit IOns; t imepreci s i on l p s ; II Net, Variable, Type, Import, Virtual Declarations II Classes ... I I Parameter Declarations . . . localparam . . spccparam . . . defparam . . . . 11 Properties, Assertions, Sequences, Coverage, Covergroups I I Nested modules etc. module . . . endmodul e interface . . . endlnLcrLace program . . . endproqram II Processes... i n itia l . always . . fi na 1 . . . . . • I I Clocking Blocks . . . clocking cbl . . . endclock i ng clocking cb2 . . . cndclocking dc!au l L clocking cbl; II Continuous assignments. . . assign X = A + B; wire (s trongl , weakO) eopynghl 0 1 995-2006 by Dou los Lid [ 3 : 0] # (2 , 3) Y 7.; 17
  • Syntax Summary I I Module instances... COMP Ul (WJ, W4 ) ; COMP U2 ( . Pl (W3) , . P2 ( W 4 ) ) ; COMP I ( 1 0 ) U3 (�13, �14 ) ; COMP I ( . Cl ( 1 0 ) ) U4 ( . Pl (W3 ) , . P2 ( �14 ) ) ; COMP US ( . Pl , . P2 , . PJ ( }) ; COMP U6 ( . • ) ; MOD U7 ( I n Lerf . slavc ) ; MOD UB ( . A ( lnterf ) , . cl k ( c l k ) ) ; 1 I Interface instances... I n t f # ( . DWIDTH ( 1 6 ) ) I n lerf (elk); I I Program instances . . . Prog Pgl (W 2 , W4 ) ; I I Bind bind M2 Prog TestProg ( . . . ) ; bind M2 I n L Bus ( . . . ) ; 1 1 Generated instances, assignments etc . genero!lte gcnvar i ; for (i=O; i < 8 ; i + + ) begin G end endgcnerate Subroutines. . . Lask . . . funclion . . . import "DPI-C" exporl " D P I -C" bind + function . . . 1I I 1 Specify Construct ... specify showcancel l ed Outl, Out2 ; pu l s es tyl e_ondcLccL Out l , Out2 ; ( A => Out l ) u ( 2 , 3 ) ; endspeci f y endmodule : M l 18 Copyoight 0 1995·2006 by Oouloa Ltd.

    Syntax Summary Interface i n l c r facc Il § (parameter i n t N 7) ( i nput logic Clk, output bil Oul, lnout bit InOut) ; t imc unit lps; 1 I Declarations, Clocking Blocks ... I I Nested interfaces and programs . . . inlerfacc 1 2 ; endlnterface; 11 Interface and program Instances . .. 12 1ntfl ( ) , I n t f 2 ( ) ; I I Tasks, Functions ... Lask . . . endtask funcLion . . . endfunction extern task Tl (inpul i , . . . ) ; extern forkjoin task T2 ( input i , . . . ) ; cxLcrn function inlegcr F ( i npuL i, . . . ) ; I I Modports . . . modport MPl ( input Rcq, Addr output Gnt , inout Data) ; modport MP2 (clocking cb) ; modporL MP3 ( import Read, Wri Lc) ; modport MP4 (exporl Task1) ; modporl MP5 ( import task Taskl (inpul i , . . .)); I I Assertions I I Continuous Assignments, Processes I I Generated instances, assignments etc. ... endinterface : Il Cop)<1911 c 19!15-2006 by Ooolos Ltd 19

    Syntax Summary Program program P i (parameter int X � 2 ) (input X, output Y, inout Z ) ; I I Declarations ... I I Clocking blocks . . . clocking cb @ (posedge Clock) ; defau l t Input # l ns output ff2n s ; inpul Y; i npuL UlsLcp UpOn output negedge Z ; - Lop.Counter.UpDn; endclocking : cb initial begin 1 1 Clocking Block Drives . .. f#l cb.Z < = 4 ' hz ; cb . Y [ l : O ] < � §#2 Tnt_Y; $exit; end 11 Assertions, Properties, Sequence, Coverage, Covergroups ... 11 Continuous assignments, Initial processes ... endprogram Declarations import a_package: : p a ckagc Lypc; import another_package : : • ; _ w i r e Wl , W2 , W 3 , W 4 ; w i r e i n t �l5; 1-12; alias IV! "This is a string" ; locaJparam Cl var V l ; v a r l ogic V2 ; reg [ 7 : 0 ] R l , Ml [ 1: 1 02 4 ] ; reg sign ed [ 3 1: 0 ] R 2 ; consl longint C 2 = 1 ; ' ( ' (0 , 1 , 2 ) , ' ( 3 ( 4 ) ) } ; i n t n[1 : 2 ] [ 1 : 3 ] • 20 Copynoht c 1995-2006 by Dou� Ltd

    Syntax Summary byle B; t ypedef logic 11 : 10] Al [!3]; s ho rtin t ST; shorLreal SR; longreal LR; enum {A, B, C) ABC; virLual inlerface an interface vi; typedef struct packed signed { inl a ; shortint b; byle c ; b i t [7 : 0] d ; Pack; Pack Ul; unio n packed Pack a cell; bil 11 : 0 ] TwoBi t ; UnionCell ; u nion tagged bit [1:0] TwoBit TwoVal ued ; logic [1 : 0 ] Tagge dCe 11; II TwoBiL FourValued; _ Associative arrays int Arra yA[']; biL [7:0] ArrayB[sLringJ; event ArrayC[AClass]; II Dynamic Arrays bit [8 : 0] DynArray1[ ] ; i n L DynArray2 I); II Queues byte byte q[S]; string upto ten names[$:9] _ _ • { "Fred", "Bill" ) ; I I Class instances AClass #{4) A; AClass #{.N{4)) B - new; BClass B = new; Bclass # ( real ) BR COpyright C 1995-2006 by Doutos Ltd. new; 21
  • Syntax Summary Subroutines I I Task declaration task automatic Tl { input A l , inout A 2 , output A3) ; I I Statements return endtask : Tl Function declaration function signed [ 7 : 0 ) Fl (input integer A l , inoul A2 , output A3) ; II II Statements F l � Expression; return Expression; endfunction : Fl I I Operator Overloading bind + iunction my_Lype add_my_type {my_type, my_type ) ; I I DPI functions and tasks import import import export "DPI-C" "DPI-C" "DPT -C" "DPI-C" function integer CFunc ( inpul i n t X); pure function real si n ( real ) ; Lask Cfunc2 { i nput in L X); SVFunc fun ction SVtoCFunc; = Classes v i rtual class ParentCl a s s ; i n t X; virtual protected function integer AFunc {byte Y) ; cndclass : ParentClass class AClass # {parameter int P 1 1 Property (data) declarations int X; static i n t Count 0; 1) extends ParentClass; ... = 1 1 Random variables rand b i t [ 1 5: 0 ) R ; randc byte RC; I I Constraints cons tra int cl { R [l : 0 ] 22 - - 2'b00;) Copyright C 1995-2006 by Doulol Ltd
  • Syntax Summary Constructor function ncw ( int X) ; this . X = X � s upc r . X; II c nctfu nc ti on I I Task, function declarations extern protected virtual II function int ExFunc ( in t Z ) ; Nested Class class ClName; endclass : ClName endclass II : AClass Member function declared outside the class functi on i n t Aclass::ExFunc (int Z ) ; e ndf u n cti o n I I C la ss with parameterised type class BClass # ( paramete r type T - inL); local T X; function AFunc ( T Y ) ; end f unc ti on e ndcl a ss Constraints c l a s s WithConstraints; rand biL xl; byte yl ; constrajnt cl ( x l -> yl -= 0;) c ons trai n t order ( s olve xl before y l ; ) c on s t ra int We i ghted { yl dist {0 := 1 . rand [ 1 :7] ·= 2} }; x2, y2 , z 2 ; constraint c { z 2 = = x2 - y2 ; } rand int rand lo gic [4:0] Addr; Copyright c 199S.2006 by Doulos Lid 23

    Syntax Summary rand enum ( low, high} type; constraint AddrRange ( ( Lype low ) -> Addr inside I ( 0 : 1 5 ] } ; ( type == high) -> Addr inside { [ 1 6 : 3 1 ] } ; endclass : WithConstrainls Processes begin : BlockName I I Statements end : B1ockNamc Forkl.abeJ : fork I I Statements join ForkLabe1 fork FB1ockNamc BcgLabel : begin I I Statements end : BegLabc1 join_any : FBlockName i n i t i al begin : BlockNamc I I Statements end always begin I 1 Statements end a lways_ comb begin I 1 Statements end a1ways_1 atch i( (Enable) begin I I Statements end 24 Cql)'Jight 0 t99S.2006 by Ooulos Ltd

    Syntax Summary a l ways_ff @ (posedgc Clk i f f Reset -- 0 or posedge Reset) begin end final begin II Statements end Statements #10 #lns @ ( A or B or C) II @ (A , B, C) @ * @ ( *) @ (posedge Cl k) @sequcncc_inst @ (Rl i f f Pl -= 1) wail (Expression) wait (A Sequcncc . Lriggered) expccl ( @ ( posedge Clock) a H#l b #Nl c ) Scrro r ( "Fai l " ) ; Reg = Expression; Reg <= Expression; Vcc LorReg [B it ] = Expression; VectorReg [ MSB: LSB] = F.xpression; VectorReg [MSB-:NBl l s ] Expression; Memory[Address] = Expression; assign Reg = Express i on deassign Reg; = return; break; continue; TaskEnabl e ( . . . ) ; $ root . MyModule . Tas kEnable ; I I Absolute name disable TaskOrBlock; -> EventName; ->>> EventName ; i f (Condit ion) else if (Condit i o n ) Copynghl c 1995-2006 by Ooulos ltd 25

    Syntax Summary else unique i f priority i f case (Seleclion) Choice] o o 0 0 0 0 Choice2, Choice3 default endcase unique case priority case . . . randcase x - I; I I Probability of executing this is 1/8 I I Probability of executing this is 3/8 3 : X - 2; 4 : X 3; II Probability of executing this is 1/2 endcase randsequence ( F i r s t ) !lead Either_Or T a i l ; First ( $write ( " Thi s is written " ) ; ) ; Head Either :• 2 I Or; E ither_Or $wriLe ( " twice" ) ; } ; E i ther $write ( " once" ) ; l; Or $di splay ( " in every three . " ) ; ) ; Tail endsequence for ( in t I-0, J•O; I*J<MAX; I�Ttl) repeat (8) while (Condit i o n ) do while (Condition) forever foreach ( uplo_Len names ( n ] ) Sdisplay ( "Name %d i s % s " , n , upto_ten_name s [ n) ) ; 26 Copyrtghl 0 1995·2006 by Oouloo Lid.

    Syntax Summary force X 1; release @ elk X; wait fork; disable fork; A5serLLabel: (All assert $display("%m passed"); else Sdisplay("'m failed"); Sequences, Prop erties and Concurrent Assertions a H#l b [*3] (a g?. b ) H#l [•5] ( a ##2 b) l'l :3] a #11 b 1 * 1 : $ ] Ul c a ##1 b[->1:3] #Hl c a llil b 1�1 : 3) 11 # 1 c (a ##1 b # # 1 c) 1-> (d #Hl c ) sequence sl (arg); @(posedge elk) a i # l b Nil c; endsequence sl and s2 sl intersect s2 sl or s2 first_malch(sl ##11:21 s?.); ['2]); x lhroughoul (##3 ((y==O)&&(z-=0 )) xl*31 within (($felly) ##1 y[*4]); sequence s3 (arg); int v; @(negedge elk) x Hill sl(v) ##1 y ##1 sl.ended #Ill z; endsequence sequence s4; @(ncgedge elk) x ##1 s2.matched [->1]##1 y; endsequence sequence s5; @(poscdge clkl) x ie @(posedge c1k2) sG; endsequence Cop)'ight 0 1995-2006 by Ooutos Ltd 27

    Syntax Summary property pl ; @ (posedge e l k ) a 1 -> b i i l c # # 1 d ; endpropcrty properly p2 ; @ (e l k ) disable iff (AFunc) not x 1 -> y Ill z; endpropc rLy property p 3 ; s 5 1 -> s5; endproperty check_pr: assert property (pr) $display("Property pr has passed" ) ; else Sdisplay ("Property pr has failed" ) ; a_imp l ies_b : assert property ( @ (posedge clock) a 1 - > b ) ; AssumeProp: assume properly ( prop ) ; CoverProp : cover property (Kesecsequence) Sdisplay ( "A reset has occurred" ) ; Covera ge enum ( Red, Green, Blue } Colour!, Colour2; covergroup cgl @ (posedge c l ock}; coverpoint Colour!; cl c2 : coverpoinL Colour2 iff ( ! Rese L l ; c3 : cross Colour!, Colour2; e ndg roup cgl cgl_jnst - new; cove rgroup cg2 (ref bit [ 9 : 0 ] v) @ (posedge clock); coverpoi n t v ( ( [ 0 : 63 ] ' 65 ) ; bins a bi.ns b [ I ( [ 1 2 7 : 1 50 ] , [ 148 : 1 9 1 ] } ; - [ 2 0 0 , 201,202 ) ; bins c [ 2 ] [ 1 000 : $ ] ) ; bins d bins oLhers [ ] - defaul t ; 28 Cop111ght C 1995-2006 by DouJos Ltd

    Syntax Summary b i t [ 9 : 0 ) v l , v2; cg2 cg2_in sL_vl cg2_i nst_v2 � new (vl ) , new (v?.) ; bit [ 4 : 1 ] v_a; covergroup cg @ (posedge elk); coverpoint v_a ( bins s a ( 4 = > 5 - > 6), ( [ 7 : 9 ] , 1 0 = > 1 1 , 1 ?.) ; bins sb[) ( 4 => 5 => 6 ) , ( [ 7 : 9 ] . 10->1 1 , 12 ) ; default sequence ; bins a llo t h e r - - endgroup CopyrlglltO 199:;.2006 by Doulos Ltd 29

    ( ' ( ' ( L L

    System Veri log GOLDEN REFERENCE GUIDE SystemVerilog Alphabetical Reference /�DOULOS

    Alias The alias statement is used to model a bi-directional short-circuit. � This feature was introduced in SystemVerilog a l i as NetLValue � NetLValue NetLValue � [= NetLVa l u e - ... ) ; { See Assig n } module-<HERE>-endmodul e l nterface-<HERE>-endi nterface generate-<HERE>-endgenerate Each signal being aliased must have lhe same net type and the same width. For example, they must both be 8-bit wires. The same nets can appear in multiple alias statements: the effects are cumulative. You are not allowed to alias a net to itself, or specify the same alias more than once. • Names need not have been declared - implicit nets are assumed. Exam les p This module reverses the bits of its bi-directional ports. module ReverscBits (inoul [7: 0 ) A, B) ; aJ ias A - {8 [ 0 ) , B [ l ] , 8 [2 ) , 8 [ 3 ] , 13 [ 4] , 8 [ 5 ] , B [ 6], 8 [ 7 ] J; endmodule In the following, semi word is implicitly declared as an 8-bit wire. wire [ 16 : 0 ] word; wi re r 7 : 0 ) halfword; a l i as word = [halfword, scmiword } ; See Also Assign 32 Cop)f;ghl Cl1995-2006 by Doulos Lid

    Always Each of the various forms of the always construct defines a static processes that contains one or more statements (procedural assignments, task enables, if, case and loop statements), which are executed repeatedly throughout a simulation run, as directed by their timing controls. The always_comb, always_latch and always_ff are used to specify design intent for simulation, synthesis and formal verification: always_comb models combinational logic behaviour; always_ff models synthesisable sequential logic behaviour; always_latch models latched logic behaviour. � always_comb, always_latch and a/ways_ff were introduced in SystemVerilog AltvaysKcyword Sta tement (one of} always always_comb always latch always_ff Al ••aysKeyword = mudule-<IIERE>-endmodule interface-<IIERE>-endtnterface genera te-<HERE>-endgenerale • Only variables may be assigned in an always etc. • Every always starts executing automatically at the start of simulation, and continues executing throughout simulation as specified by any timing controls. When the last statement in the always is reached, execution continues from the top of the always. always_comb and always_latch statements are executed automatically once at the start of simulation, after all initial and always statements have executed. always_comb and always_latch have inferred sensitivity lists, which include all variables read by the procedure and called functions. They may not have blocking timing or event controls. An always_ff must have exactly one event control and no blocking timing controls. The variables on the left-hand side of assignments in an always_comb, always_ff or an always_latch, including variables from the contents of a Copy!ighl C 1995-2006 by Doolos ltd 33

    Always called function, may not be written to by any other process. (always @* and always @(*) allow multiple processes to write to the same variable.) always_comb and always_latch can include neither statements that block nor fork-join blocks. Gotchasl • An always containing more than one statement must enclose the statements in a begin-end or fork-join block. • An always with no timing controls will loop forever. • In RTL code, use only the always_comb, always_latch and always_ff statements, so that the tools can check the style of the code matches the intent. Exam les p The following example shows an always which describes combinational logic: always @ (A or B or C or D) begin R � { A , B, C , D ) F 0; begin : Loop integer I ; for ( I = 0 ; I < 4 ; I Equiv. to @(*), @*, or @(A, B, C, D) II = I I 1} (R[II ) begin F I; disable Loop; end jf - end end II Loop The following example shows an always_comb: al ways_comb A = 13 & C; always_comb A <- # l Ons 13 & C; 34 COpyrtghl 0 1995-2006 byDoulos Ltd

    Always The following example shows an always_ff: always_ff @ (poscdge Clk i f f Reset -- 0 or posedgc Reset) begin end The following example shows an always_latch: always_laLch i i (Enable ) Q <= D; The following example shows an always_ff: always_ff @ (posedge Clock i f f nReset or negcdge nRcseL) begin i f ( ! nReset) Count <- 0 ; I I Asynchronous reset else if ( ! Load) Count <- Data; I I Synchronous load else Count <- Count 1 1 ; end See Also Begin, Final, Fork, Initial, Statement, Timing Control Copynght0 199S.2006 b)' Douloo Ltd 35

    Array SystemVerilog supports fixed-size, dynamic and associative arrays. Fixed-size arrays can have an arbitrary number of dimensions. Dynamic and associative arrays are one-dimensional. Array elements can be of any type and bit-select, part-select and array slicing operations are possible . .,.. Arrays are enhanced in SystemVerilog; dynamic and associative arrays were introduced in SystemVerilog 1 Declaration } Da ta Type PackedDimcns ions . . Nurnc Unpa ckedDimensions . . . [ , Name Unpa ckedDimensions ]; . . . . PackcdDimcnsi on = UnPackcdDimensi on [ Cons LantExpression : Constan tr:xpression] = tone of} [Constan tExpression] [ConsLan tExpression: Constan tExpression] { Use } 1rrayElement [Express ion+ : Cons t a n L Expression] { Whole array} {slice} { Var iable slice } ArrayElemen t [ Expression- : Cons tan tExpressi on] { Variable slice } ArrayName ArrayElemen t [ Cons tan tExpressi on: Cons tan LExpression ] ArrayEl ement = ArrayName [ [ I xpressi on ] [ [ Expression] ·: . . . J] ( Element ) p Packed and Un acked The term "packed array" is used to refer to the dimensions declared before the object name. The term "unpacked array" is used to refer to the dimensions declared after the object name. The packed dimensions correspond to the "vector width" in Verilog. A packed array is guaranteed to be represented as a contiguous set of bits. A single array may have both packed and unpacked dimensions. bit ( 7 : 0 ] B ; I I Packed array real R I I Unpacked array [7 : 0] ; • It is possible to create arrays of nets, var iables, object handles and events. • Both packed and unpacked arrays can be multi-dimensional. 36 Cop)flgl1 0 1995-2006 by Daulos Ltd

    Array One dimension of an unpacked array can be declared as having a un-fixed (dynamic) size. The size is specified at runtime using the new operator. An unpacked dimension can be expressed as a single number, as in C. E.g. [ s i zc] . This is equivalent to [ O : size-1 ] . I I Equiv. to: b i t A [ 0 : 3 J I 0 : 7 ] ; In a list of dimensions, the right-most one varies most rapidly. However, a packed dimension varies more rapidly than an unpacked one. bit A [ 4 ] [ 8 ] ; log i c [ 0 : 1 5 ] T1 [ 0 : 7 ] ; logic A2 [ 0 : 7 ] l ogic [ 0 : 7 ] • [ 0 : 15 ] ; [ 0 : 1 5 1 A3; 1 I [0: 1 5 ] varies most rapidly 1 1 [0:15] varies most rapidly 1 1 (0:15) varies most rapidly A single element of a packed or unpacked array can be selected using an indexed name. This element may itself be an array. bil [ 3 : 0 ] byte A ; [ 7 : 0 ] PackedArr:ay; B = PackcdArr:ay [ ? ] ; 1 I Select a single 8-bit element • An X or Z in an index expression, or an index which is out of the address bounds, causes a read to return X (for 4-state types) or 0 (for 2-state types). In either case, a run-time warning is issued. Writing to an array with an invalid index will perform no operation. • One or more adjacent elements can be selected using a slice name. A slice is a selection of one or more adjacent elements of an array, whereas a Part-select is a selection of one or more adjacent bits of a single dimension packed array. The size of the slice or part-select must be constant, but the position may be var iable. Slices of an array can only apply to one dimension - other dimensions must have single index values in an expression. • Assignment patterns may be used for array initializers, literals and expressions. The expressions must match element for element and the braces must match the array dimensions. Each element must match the type being initialized. bi. t UnpackedArr:ay1 [ 1 : 0 ] - ' { 1 , 1 J I I No size warning, bit can i n t UnpackedAr:r:ay2 [ 1 : 0 ] I I be set to 1 ' { 1 ' b 1 , 1 ' bl } ; Packed Arra Rules y • If a packed array is declared as signed, then the array viewed as a single vector is signed. A part-select of a packed array is unsigned, and the individual elements are unsigned unless they are of a named type declared as signed. Copyngllt C) 1995-2006 by Doulos ltd 37

    Array Packed arrays allow arbitrary length integer types. The maximum size of a packed array may be limited, but must be at least 2**16 bits. • Packed arrays can only be made of the single bit types: bit, logic, reg, wire and the other net types and using other packed arrays and structs. • A packed array cannot be assigned to an unpacked array without an explicit cast. A slice name of a packed array is a packed array. • The following operations can be performed on packed arrays only: Assign an integer (e.g. A • • = 8 ' bl l l l l l l l ; ) Treat as an integer in an expression (e.g. ( A + 3)) Integer types with predefined widths (i.e. byte, shortint, int, longlnt, and Integer) cannot have packed array dimensions declared. They can be treated as a single dimension packed array, with the dimension numbered down to 0. byte B ; I I Equiv. to b i L [ 7 : 0 ] B; i n Leger I ; I I Equiv. to 1 ogic signed [ 31 : 0 J r; Unp acked Arra Rules y An unpacked array cannot be viewed as a single vector. Therefore if it is declared as signed, that means that each individual element of the array is signed. • An element of an unpacked array may be a packed array. • Unpacked arrays can be of any type. • A slice name of an unpacked array is an unpacked array. bit Ar.rayl [ 7 : 0 ] inL Array2 Array2 = [15:0] [3:0] ; Arrayl [ 3 : 0 ] ; 1 1 Array of 8 1 5-bit vectors I I Array of 4 ints 1 I Slice from Array1 A number of system functions provide information about arrays: $left, $right, $low, $high, $increment, $size and $dimension. Multiple array dimensions can be defined in stages using a typedef: typedef bil [ 1 : 5 ] fivcb i ts; fivebits [ 1 : 10 ] f ; 1 1 Equivalent to bit [1 : 10)[1 :5] f; typcdef Fivcbits mern_ Lype [ 4 ] ; mem_typc mem ( 8] ; I I bit [1:5] mem [3:0][7:0]; 38 Copyright 0 199!>-2006 by Ooulos ltd

    Array Exam les p wire [7 : 0 ] A [ 0 : 15] [0 : 15 ] , B [ 0 : 15] [0 : 15] ; I I Two 16x16 array of bytes / [ O J [ 1 ] [ 2 ] B [ 1 ] [2] [ 3 1 ; I I Bit-select A = B; logic [ 1 5 : 0 ] 1rrayl ; l og i c [ 7 : 0 ] Array2; Array2 Array1 1 8 : 1 ] ; � I I Part-select Reading and writing a variable slice of the array A [ x+ : c] = B [y+ : c ] I I c must be constant Multiple packed dimensions defined in stages using typedef typedef b i L [ 0 : 7 ] BB; BB [ 0 : 1 5 ] B8_1 6 ; I I [0:7] varies most rapidly Multiple unpacked dimensions defined in stages using typedef typedef BB Mem[ 0 : 3 ] ; I I Array of four BB elements Mem Mcrn8 [ 0 : 7 ] ; I I Array of 8 Mem elements Sea Also Array Manipulation Methods, Associative Array, Dynamic Array, Generate, Instantiation. Module, System Tasks and Functions, Queue Copyr'!Jhl C> 1 !195-2006 by Ooulos ltd 39

    Array Manipulation Methods There are a number of built-in methods, which may be used to search, sort and reduce arrays. ""' This feature was added in SystemVerilog 1 Calling a method 1 1J:rayName . MethodName [ (Arguments, . . . ) I [with ( Expression) ] Array Locator Methods Locate specified elements of an unpacked array or queue. These return a queue of the same type as the array being operated on. Prototype: function ArrayType [$] Method ( ArrayType Iterator item) ; The wi Lh clause is mandatory for these: find ( ) Returns all the elements satisfying the given expression find_first ( ) Returns the first element satisfying the given expression f i nd_last ( ) Returns the last element satisfying the given expression The w i t h clause is optional for these: Returns the element with the minimum value or where the ., i th expression evaluates to a minimum min ( ) Returns the element with the maximum value or max ( ) the with expression evaluates to a maximum Returns all elements with unique values or whose uniqu e ( ) with expression is unique Array Index Locator Methods Locate specified elements of an unpacked array or queue. These return a queue of the array's index type, which is always int, except for associative arrays. Prototype: func t i on Type [ $ ] Method ( ArrayType Iterator = item ) ; The with clause is mandatory for these: Returns the indexes of all the elements satisfying the find_index ( ) given expression find_f i rs t_index ( ) Retums the index of the first element satisfying the given expression 40 Copynoht 0 1995-2006 by D0<1tos ltd

    Array Manipulation Methods find l a s t index ( ) Returns the index of the last element satisfying the given expression The with clause is optional for this: unique index ( ) _ Returns the indexes of all elements with unique values or whose with expression is unique Array Orderin Methods g Reorder the elements of a one-dimensional array or a queue. Prototype: funcLion voi d McLhod (ArrayTypc Iterator - item) The with clause is prohibited for these: Reverses all the elements of the array reverse ( ) shuffle ( ) Randomizes the order of the elements in the array The w i th clause is optional for these: sort ( ) Sorts the unpacked array in ascending order rsort ( ) Sorts the unpacked array in descending order Arra Reduction Methods y Reduce any unpacked array to a single value, whose type is the element type. Prototype: funcLion Type MeLhod (Arra y1'ype ilcrator i Lcm) The with clause is optional for all these: sum ( ) Returns the sum of the array's elements or the sum of the wi th expressions product ( ) Returns the product of the array's elements or the and ( ) product of the w i th expressions Returns the bitwise AND of the array's elements or the or() bitwise AND of the with expressions Similarly, returns the bitwise OR xor ( ) Similarly, returns the bitwise XOR ue in lterator Index Q ry g Method Returns the index of an array iterator in an array manipulation wi Lh expression. The return is always int, except for associative arrays. Prototype: function Type index ( int Dimension Copynght Cl 1995-2006 by Doulos Ltd 1) 41

    Array Manipulation Methods In the min(), max(), unique() and unique_index() locator methods the with clause and its expression may be omitted if the relational operators (<, >, ==) are defined for the element type of the given array. If the with clause is used, the relational operators must be defined for the type of the expression. • Gotchasl The optional with clause accepts an expression enclosed in parentheses. In contrast, the with clause used by the randomize method accepts a set of constraints enclosed in braces. Exam les p byte b [ 1 = ' { 1, 3, 2l ; i n t ,.; , r [ $ ] ; r � b . fi nd ( x ) w i th r � b . f ind with (x > 2 ) ; ( i tem I I r = (3} i Lcm . index) ; I I find all items equal to their I I index, i.e. (1} r = II r= 1 b . min; II b = b . sort; s = b . sum with = '(2, 3, 1 } '{1, 2 , 3} I I s = 1 8 (i.e. 5 + 7 + 6) I I s= 0 (i.e. 1 " 3 " 2) II b b . rcvers e ; ( i tem + 4 ) ; s � b . xo r ; Find all items in Ar1 that are greater than corresponding item i n Ar2 Ar2 [ 3 : 0 ] [ 3 : 0 1 ; in L r [ S J ; r = Arl . find ( x ) with ( x > Ar2 [ x . indcx ( l ) ] [ x . i ndex ( 2 ) l l ; i n t Ar l [ J : O ] [ J : O ] , See Also Array, Queue 42 Copyright C 1995-2006 by Ooutos ltd.

    Assert An assertion is a statement that something must be true. assert property can be used as a concurrent or procedural statement. An immediate assertion is evaluated during the execution of procedural code, such as the statements in an always block. For a concurrent assertion, variables are sampled when a specified clock event occurs. II> This f eature was added in SystemVerilog { Immediate assertion J {AsscrtJ.abcl : ] a!lserl (Expression) { Concurrent assertion J [Asscrtl.abel : ] asserl property AcLionBlock ; ActionBJock ( ProperLySpec) ActionB I ock [one of) Sta tement [ S ta t emen t] else SLa temen tOrNull Prope r LySpec ; see Property For Immediate Assertions see Statement. For Concurrent Assertions: always -<IIERE> i n l t i a l-<HERE> module-<IIERE>-endmodulc genera Le-<IIERE>-endgenera le inLerface-<HERE>-endinterface program-<IIERE>-endprogram • Being a statement, the immediate assert can be used anywhere a statement can be used in procedural code. • The expression tested in the immediate assert statement is non-temporal and treated as an expression in the condition of a procedural if statement. • There is a severity associated with the failure of an assertion (see Assertion Severity System Tasks). The default one is "$error". • A named assertion can be disabled. Copynghl C 1995-2006 by Doulos Lid 43
  • Assert assert property statements executed outside procedural code are executed throughout simulation. • The assert property statement is used to enforce a property as a checker. When the property is evaluated as true. the pass statement (if any) of the ActionB/ock is executed. Otherwise, the fail statement is executed. When no action is needed, a null statement (i.e. ;) is specified. If no statement is specified for the else. then $error is used as the fail statement of the ActionBlock. • The ActionBiock of a concurrent assertion cannot include any concurrent assert. assume or cover statement. but it can contain immediate assertion statements. • The clock for an assert property statement is determined as follows: Any explicitly specified clock for the assertion. • Else. it is the inferred clock from the context of the code when embedded. Else, the default clock. if specified. • A multi-clocked assert property statement must not be embedded in procedural code where a clock is inferred. It must have the clocks explicitly specified. • Label all assertion statements. The assertion label can be displayed using the %-m format code. AssertLabcl : assert (Exp) Sdisplay ( " %m passed" ) ; else $displa y ( "%m failed " ) ; • The fail statement can be used to signal a failure to another part of the testbench. • Immediate assertions can be used to document assumptions. while concurrent assertions can be derived from the design's specification and used to verify correct functioning. 44 COpyngl1 C 199S.2006 by Ooulos Ud.
  • Assert Exam les p Immediate assertions always @ (posedge el k) assert (State ! - I llegal_Stale) else $error ( " I l legal state reached" ) ; inilial begin assert ( A -= B ) ; assert (C && D) Sdisplay ( "OK - C and D are both true " ) ; assert (E) else $warning ( " � is NOT true" ) ; end Concurrent assertions module FlipFlop ( inpul logic elk, D, outpul logic Q) ; property P2; inL d ; d) ; @ (posedge e l k ) ( 1 , (d=D) ) 1 -> R 1 1 (Q endproperly Label2 : assert property ( P 2 ) ; always @ (posedge elk) Q <= D; endmodule I I Module Flipfiop above is equivalent to modul e FlipFlop ( input logic e l k , D, output logi c Q) ; properly P2 ; i nl d; d) ; ( 1 , (d=D) ) I -> # H l ( Q endproperty always @ ( posedge elk) begin I�bel 2 : assert property (P2 ) ; Q <= D; end endmodule See Also Assume, Bind, Cover. Disable, Expect, Property, Sequence, System Tasks and Functions, Wait Copynght C> 1995-2006 by Ooutos Ltd 45
  • Assign Assign outside any initial or always statements creates a continuous assignment to one or more nets or variables. Events are created on the assigned nets or variables whenever an expression changes value. Assign in an initial or always is a procedural continuous assignment. When active, this creates a continuous assignment to one or more variables, and prevents ordinary procedural assignments from affecting the values of the assigned variables. Procedural assign and deassign statements may be removed from future versions of the language. Ill- SystemVerilog adds the ability to assign variables { Continuous assignment - one of} assign [ S trength] [ Delay3J NetLValue = NeLLValue . . . Expr-ession, Expressi on , ; f.'xpression, assign [ DelayControl] VariablcLValue Va r:iableLVaZue � Expression . . . ; { See also Net 1 { Procedural continuous assignment - one of} a s s i gn Vari ableLValue ExpLcssion; deassign VariablcLVa l u e ; = Delay3 = { one of} H DelayValue # (Min typmaxExp ression NeLLVa l u e � ( , Min t ypmaxExpression, .. .] ) {one of} NctName NetAr:ray { NetLValue, . . . ) • { Neti.Value, . . . ) NetArray = See Array see Timing Control DelayConLrol - variablci.Val u e = see Procedural Assignment Continuous assignment module-<HERE>-endmodule inter face-<IIERE>-endinterface program-<IIERE>-endprogram genc raLe-<HERE>-endgenera te 46 Cop)Tight 0 1995-2006 by Doulol lld

    Assign Procedural continuous assignment - see Statement. Continuous assignments can drive nets or variables. The strength specification is not allowed with variables. A variable may be assigned using one continuous assignment or driven from a single output port. Such variables may not be initialized nor assigned using a procedural assignment. They may not be driven from more than one continuous assignment, from more than one output port, or a combination of these. A continous assignment is evaluated at time 0. The nets on the left-hand side of an assign are declared implicitly as wires if they have not been declared explicitly. This can be prevented by using the compiler directive "default_nettype none. Alternatively, a different default net type may be specified. After it is executed, a procedural continuous assignment remains in force on the assigned variable(s) until it is deassigned, or until another procedural continuous assignment is made to the same variable. A force on a variable overrides a procedural continuous assignment on that variable, until it is released, when the procedural continuous assignment again takes effect. Gotchas! Continuous assignments are not the same as procedural continuous assignments, although they are similar. Make sure that you place assign in the correct place. A continuous assignment goes outside any initial or always. A procedural continuous assignment goes where statements are allowed (inside Initial, always, task, function etc.). Use continuous assignments to describe combinational logic that can easily be described using a straightforward expression. Functions can be used to structure expressions. An always is usually better for describing more complex combinational logic, and may simulate more quickly than a number of separate continuous assignment statements. Continuous assignments are useful for transferring variable values to nets, when SystemVerilog requires nets to be used. For example, to apply test stimulus described in an initial to an inout port of a module instance. Cop)<ight c 199:;.2006 by Ooutos Ltd 47

    Assign • Procedural continuous assignments are deprecated and may be removed in a future version of SystemVerilog - don't use them! Exam les p Continuous assignment 11j re wire cout, c:in; [ 3 1 : 0] as sign sum, b; a, ( c o u L , sum} = a + b + cin; Procedural continuous assignment always @ (posedge Clock) Counl � Count + 1 ; 1 I Asynchronous Reset a l ways @ (Reset) if (Reset) assign Count = 0; 1 1 Prevents counting, until Reset goes low else deas sign C o u n t ; 1 1 Resume counting on next posedge Clock See Also Force, Net 48 Cop)l'lghtC 1995·2006 by Doutos Ltd.

    Associative Array An associative array implements a lookup table. The index type need not be integral. Storage is only allocated when it is used. Associative arrays are useful when the distribution of the data that is to be stored in an array is sparse. ll> This f eature was added in SystemVerilog Da ta Type Name [Da t a Type] ; Da liJ 1'ype Name [ * J ; 1 Index is any type 1 { Index is arbitrarily-sized integer) ( Methods) in t num ( ) ; funclion void delete ( [ i nput Index ] ) ; function i n t exists ( i np u t Index ) ; function i n L fi r s t ( ref I ndex) ; function i n t last ( r e f Index ) ; funclion i n L nexL ( re f I ndex) ; function i n t pr ev ( r e f Index ) ; function Where Index is an index value of the appropriate type. Methods num() - returns the number of indexes in the array. delete((lndex]) - deletes the specified index or (if an index is not specified) the whole array. exists(lndex) - true if an entry for the index exists. first(lndex), last(lndex) - assigns the first (last) index in the array to Index and returns 1 , or 0 if the array is empty. • next(lndex), prev(/ndex) - assigns the next (previous) index in the array to Index and returns 1 , or 0 if there isn't a next (or previous) entry. There are several other methods that apply to all arrays, including associative arrays (see Array Manipulation Methods). • For an integer or for the wildcard index type, a 4-state index containing X or Z is not allowed. • An empty string is valid as an index of type string. A null index is allowed as an index of a class type. An associative array can only be assigned to another associative array that has a compatible type and the same index type. Cop)1ight c 1995-2006 by Douloo Ltd 49

    Associative Array Associative array literals use the syntax '{index : value} or '{default : value} (See examples). • Associative array elements are unpacked, meaning that an individual element must be selected out of the array before using it in most expressions (apart from copy or comparison expressions). • An associative array allocates storage for elements individually as they are written. Associative arrays can be indexed using arbitrary data types. Exam les p Create an array of integer, indexed by string integer CounLWords [ s t r i n g ) ; CounLWords [ "one" ] I + ; Sdisplay ( " Therc a r e % d d i f ferent words " , CountWords . num) ; CountWords . delete ( "one" ) ; I I Deletes the "one" entry CountWords . dcJete; I I Clears the entire array Create an array of string, indexed by integers s l r i ng Table [ * ) ; Table ; ' { O : "Zcro " , l : "One " , 2 : "Two " , defaul t : "None " ) ; Sdi splay < " % s %s " , Table [ 0 J , Table [ 3 J l ; I I Displays "Zero None" See Also Array, Array Manipulation Methods, Dynamic Array 50 CopynghtC 1995-2006 by Oootos lld

    Assume Assume property is used to specify a property as an assumption for formal analysis. In simulation, an assume property is like a concurrent assertion that checks the behaviour of the testbench. Assume property can be used as a concurrent or procedural statement. .,.. This f eature was added in SystemVerilog [ AssumeLabcl : ] assume property PropertySpec ( PropertySpec) ; see Property always-<IIERE> i ni t ial -<IIERE> module-<IIERE>-endmodule gcnerale-<IIERE>-cndqeneralc i nLcrfacc-<HERE>-endi nterface program-<IIERE>-cndprogram For formal analysis, there is no obligation to check that the assumed properties hold. For simulation, the environment must be constrained such that the properties that are assumed will hold and the simulator must report if the property fails. • For random simulation, a dist constraint provides weights for choosing random values. This is called biasing. Gotchasl Assume property does not provide an action block, as the actions for an assumption serve no purpose. Exam les p al : assume property ( @ (poscdge elk) ack 1 -> ! ack) ; a2 : assume prope r l y ( @ (posedge elk) req d i s L ( 0 : -1 , 1 : -9 } ) ; See Also Assert, Constraint, Cover, Property Cop)Tight C> 1995-2006 by Dooloo Ltd 51

    Attribute Mechanism, not hidden in comments, used to specify properties about objects, statements and groups of statements in the source code. It may be used by various tools, including simulators, to control the operation or behaviour of the tool. Attributes are tool-specific and their meaning cannot be part of the language standard. (• A c c ribuLeSpecs, . . . • ) {one of} AttributeNarnc = Cons tanLExpression AttributeName A L t r i b u ceSpcc - As a prefix attached to ANY declaration, a module item, a Statement, a port connection, or an interface item (including modport). • As a suffix to an operator or a SystemVerilog function name in an expression. NOTE: As attributes may be specified almost anywhere, they are not included in the syntax descriptions in the Golden Reference Guide. All tools are required to process the attributes, so that any tool that does not understand an attribute must at least displa

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