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SimulatorsOverview

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Information about SimulatorsOverview
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Published on February 18, 2008

Author: Raimondo

Source: authorstream.com

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Slide2:  Concept Performance Evaluation Performance Evaluation:  Create a Model Appropriate Workloads Measure Performance Evaluate Performance Performance Evaluation Model:  Model Hardware Model Software Model Too Complex and Time Consuming Not very Precise but very Efficient Hardware Simulator:  Hardware Simulator What does a Simulator do?:  What does a Simulator do? What has it got to offer?:  What has it got to offer? Slide8:  Architectural Simulators Functional Performance Trace Driven Execution Driven Instruction Schedulers Cycle Timers Interpreters Direct Execution Source: SimpleScalar Hacker's Guide and SimpleScalar 4.0 Tutorial by Todd Austin Purpose of a Simulator:  Purpose of a Simulator Classification of Simulators:  Classification of Simulators Single Processor Performance Simulators:  Single Processor Performance Simulators SimpleScalar:  SimpleScalar M-Sim:  M-Sim M-Sim:  M-Sim Full System Simulators :  Full System Simulators Simics:  Simics Simics:  Simics Fastest In-order processor Single cycle execution latencies Compromise or optimize? Scaled back version of the out-of-order model No user visible API number of instruction execution options reduced. Slowest Detailed out-of-order model Allows the user to specify a detailed timing model and manner of instruction execution. Simics:  Simics SimOS:  SimOS SimOS:  SimOS Source: http://simos.stanford.edu/ Power Consumption Simulators :  Power Consumption Simulators Wattch:  Wattch Wattch:  Wattch The Others…:  The Others… Multiprocessor Simulators:  Multiprocessor Simulators RSIM:  RSIM The M5:  The M5 The M5:  The M5 Modular Simulators:  Modular Simulators Solution? Use of modular Simulators Liberty Simulation Environment (LSE) :  Liberty Simulation Environment (LSE) Asim:  Asim Benchmark suites:  Benchmark suites General Purpose Benchmark Suites :  General Purpose Benchmark Suites Embedded Benchmark Suites:  Embedded Benchmark Suites Miscellaneous Benchmark Suites :  Miscellaneous Benchmark Suites SimpleScalar Revisited:  SimpleScalar Revisited SimpleScalar:  SimpleScalar Interpreters:  Interpreters Tools available in SimpleScalar:  Tools available in SimpleScalar Architectural Simulators Functional Performance Trace Driven Execution Driven Instruction Schedulers Cycle Timers Interpreters Direct Execution Source: SimpleScalar Hacker's Guide and SimpleScalar 4.0 Tutorial by Todd Austin Baseline Simulator Models:  Baseline Simulator Models Sim-fast:  Sim-fast Functional simulation Optimized for speed Assumes no cache Does not support DLite! Does not allow command line arguments Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani Sim-safe:  Sim-safe Functional simulation Checks for correct alignment and access permissions for each memory reference Optimized for speed Assumes no cache Supports DLite! Does not allow command line arguments Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani Sim-cache:  Sim-cache Cache simulation Ideal for fast simulation of caches If the effect of cache performance on execution time is not necessary Accepts command line arguments for: Level 1 & 2 instruction and data caches TLB configuration (data and instruction) Flush and compress Ideal for performing high-level cache studies that don’t take access time of caches into account Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani Sim-cheetah:  Sim-cheetah Cache simulation Originated at UMich Simulates fully associative cache efficiently Simulates a sometime-optimal replacement policy (MIN) MIN or OPT use future knowledge to select a replacement Accepts command line arguments Max size of cache Replacement policy – LRU, OPT Fully associative, set associative, or direct mapped cache Ideal for performing high-level cache studies that don’t take access times of caches into account Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani Sim-bpred:  Sim-bpred Simulate different branch prediction mechanisms Generate prediction hit and miss rate reports Does not simulate the effect of branch prediction on total execution time Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani Sim-profile:  Sim-profile Program profiler Generates detailed profiles, by symbol and by address Keeps track of and reports Dynamic instruction counts Instruction class counts Branch class counts Usage of address modes Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani Sim-outorder:  Sim-outorder Most complicated and detailed simulator Supports out-of-order issue and execution Provides reports Branch prediction Cache External memory Various configurations Adapted from “SimpleScalar Introduction for toolset release v2.0” by Praveen Bhojwani DLite! Debugger:  DLite! Debugger Lightweight symbolic debugger Supported by all simulators except sim-fast Parting Words…:  Parting Words… Released with a noble cause in mind. Toolkit is well documented. Includes baseline models. Ideal toolkit for microarchitecture simulation. Conclusions:  Conclusions Simulation is often the only practical way to test architectural ideas and assess system performance. Offer flexibility to modify and analyze the impact of various architectural parameters and components. Various types of simulators available along with the benchmarks used to evaluate the performance of a design. Discussed SimpleScalar. Future Work:  Future Work Focus on various simulation methodologies and statistical approaches to the processing of the results. Model a new architectural concept in one of the simulators and analyze and compare its performance. References:  References J. Yi and D. Lilja, "Simulation of Computer Architectures: Simulations, Benchmarks, Methodologies, and Recommendations," IEEE Transactions on Computers, Vol. 55, No. 3, March 2006. T. Austin, E. Larson, and D. Ernst, “SimpleScalar: An Infrastructure for Computer System Modeling,” Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002. Joseph Sharkey, "M-Sim: A Flexible, Multi-threaded Architectural Simulation Environment" Technical Report CS-TR-05-DP01, Department of Computer Science, State University of New York at Binghamton, Binghamton, NY, October, 2005. P. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Halberg, J. Hogberg, F. Larsson, A. Moestedt, and B. Werner, “Simics: A Full System Simulation Platform,” Computer, vol. 35, no. 2, pp. 50-58, Feb. 2002. http://simos.stanford.edu/ D. Brooks, V. Tiwari, and M. Martonosi, “Wattch: A Framework for Architectural-Level Power Analysis and Optimizations,” Proc. Int’l Symp. Computer Architecture, 2000. W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, The design and use of SimplePower: a cycle-accurate energy estimation tool, In Proc. Design. Automation Conference (DAC), Los Angeles, June 5-9, 2000. C. Hughes, V. Pai, P. Ranganathan, and S. Adve, “Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors,” Computer, vol. 35, no. 2, pp. 40-49, Feb. 2002. S. Herrod. Tango lite: A multiprocessor simulation environment. Technical report, Computer Systems Laboratory, Stanford University, 1993. http://m5.eecs.umich.edu, 2006. M. Vachharajani, N. Vachharajani, D. Penry, J. Blome, and D. August, “Microarchitectural Exploration with Liberty,” Proc. Int’l Symp. Microarchitecture, 2002. J. Emer, P. Ahuja, E. Borch, A. Klauser, C. Luk, S. Manne, S. Mukherjee, H. Patil, S. Wallace, N. Binkert, R. Espasa, and T. Juan, “Asim: A Performance Model Framework,” Computer, vol. 35, no. 2, pp. 68-76, Feb. 2002. Thank you!!!:  Thank you!!! Questions ???

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