Sigma delta poster by David Sobel

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Information about Sigma delta poster by David Sobel

Published on January 8, 2008

Author: Dante


High-speed Sigma-Delta Analog-to-Digital Conversion for Indoor Wireless Systems:  High-speed Sigma-Delta Analog-to-Digital Conversion for Indoor Wireless Systems David A. Sobel Prof. Robert W. Brodersen Berkeley Wireless Research Center Dept. of EECS UC-Berkeley Introduction:  Introduction System Specifications for ADC 25 Ms/s Nyquist rate. (Tchip = 40ns) Approx. 6-8+ bits dynamic range. see C. Teuscher, “Low Power Receiver Design for Portable RF Applications…,” Ph.D. thesis, UCB ’98 Sampling offset granularity < Tchip/2. Choice of converter architecture Specification met with pipeline converter see G. Chien, “High-Speed, Low-power, Low-Voltage, Pipelined A/D Converter,” MS thesis, UCB ’96. High fT of 0.25mm CMOS makes sigma-delta (SD) architecture feasible. Motivation for SD Converter:  Motivation for SD Converter Leverage off of increasing fT of CMOS process. fNYQ of high-resolution SD’s > 2 MHz. Decreased sensitivity to analog mismatch and other imperfections Calibration or digital correction not necessary. Oversampling eases requirements of supporting analog filtering. Oversampling decreases area used by passives. D is a “mostly digital” converter Robust, programmable digital channel-select filters Opportunities for system/circuit co-design. SD-assisted Timing Recovery:  SD-assisted Timing Recovery Tchip/8 sampling offset granularity with A/D running at Nyquist Architectural modifications can reduce filter bank complexity with an increase in stream-switching latency Delay line z-1 z-1 z-1 FIR & Decimation FIR & Decimation FIR & Decimation Multiplexer Stream Control to Data Correlator Timing Recovery Blocks Filter bank Timing Recovery from 8x OSR SD modulator up to 8 parallel streams Code-based Noise Shaping:  Code-based Noise Shaping Equivalence of FDMA and CDMA systems Both systems divide bandwidth into N subsets. Only difference is basis of N-dimensional space. SD modulators “shape” noise out of desired subset FDMA systems shape q-noise into other frequency band. Can we extend this to CDMA? First concept: Analog PN-sequence. Achieves effective oversampling of M*N. High-Speed SD Architecture Considerations:  High-Speed SD Architecture Considerations High-speed SD: low-oversampling (OSR). Low-OSR: high order, multi-bit SD. High-order SD: Single-loop vs. cascade Single-loop high-order modulators can be unstable Cascade SD’s more sensitive to analog non-idealities; interstage coupling amplifies noise. Single-bit vs. multibit quantization Multi-bit converter reduces quantization noise Multi-bit DAC in first stage must be highly linear. Non-linearity of multi-bit DAC in later stages is shaped. SD Architecture and Static Power Dissipation:  SD Architecture and Static Power Dissipation Typical SC integrator: PSTAT without parasitics: PSTAT with parasitics: VIN CS CGS CL CI VOUT 2-1-1 Cascade Architecture:  2-1-1 Cascade Architecture Architecture Choice: 2-1-1 cascade. OSR=8. 1-bit quantization in all stages DR = 47 dB Coefficient Selection Small coefficients alleviate speed constraints. Thermal noise not dominant. ò ò S S DAC Y 1 0.33 0.6 -0.4 – 0.33 – DAC ò S 1/3 – 1/3 1/3 – DAC Y 3 ò S 0/5 – 5/6 1/3 – Y 2 V IN Structural System Modeling, SD Modulator:  Structural System Modeling, SD Modulator Quantization noise Thermal noise Finite DC gain Capacitor mismatch Comparator offset, hysteresis Transient response integrator comparator SD and Downlink block-level simulation:  SD and Downlink block-level simulation Circuit blocks modelled in SIMULINK. D simulated as part of entire downlink. SNR of complete downlink (SIMULINK model) Circuit Design:  Circuit Design Integrators Speed requirement dominant; low gain requirement. NMOS folded cascode topology: Av0 = (gmro)2 is sufficient. NMOS input for maximum speed. Folded cascode for swing. Sufficiently stable. Developed optimization routine to minimize power. Switches VGS limited to 2.5V. Process not tolerant of standard bootstrap. “Constant VGS bootstrap” loads signal path. CMOS switches utilized. Increased clock power. Comparator High input offset, hysteresis tolerable. Low-power dynamic comparator used Simulation Results:  Simulation Results Simulated DR: 47 dB Q-noise limited 25 Ms/s Nyquist rate Linear to “numerical noise” Power dissipation: 26 mW 11 mW analog circuitry 15 mW digital circuitry Chip back from fab Jan ’00

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