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Published on January 22, 2008

Author: Silvia

Source: authorstream.com

“Workshop on Spacecraft Data Systems” :  “Workshop on Spacecraft Data Systems” COTS-based activities on Spacecraft Data Systems by IMT G.Perrotta, G.Cucinella IMT srl, Via Carlo Bartolomeo Piazza 8 00161 - Rome, Italy e-mail: imtsrl@iol.it - URL: www.imtsrl.it IMT’s activities:  IMT’s activities The on-going IMT’s activities on Spacecraft Data Systems are: - a COTS-based on board computer; -a COTS-based multi-terabyte RAID system. The On-Board Computer:  The On-Board Computer The initial IMT’s idea of building an OBC with COTS boards was sponsored by ESA through a contract (N.13409/98/NL/MV) which enabled to test the radiation and environmental endurance capabilities of motherboards made by two different Italian vendors leading to the selection of one. The success of this contract led to an ASI contract (N. I/180/01/0 as co-funding) for the realisation of a full COTS-based On-Board Computer (OBC) including the updating of the motherboard, the addition of the I/O and SCC (synchronous Serial Communication Controller) boards, and of the additional 1GB mass memory (based on flash EPROMS). The On-Board Computer - The OBC features:  The On-Board Computer - The OBC features PC/AT architecture, efficiently packaged on PC 104 cards. It includes an ELAN 520 133 MHz CPU board by SECO (an Italian PC104 boards Supplier) provided with 32 MB DRAM. Memory card with a Flash EPROMS of up to 1 GB memory. Board providing two full-duplex high speed serial channels. I/O board providing 16 analogue input channels, 2 output channels, 8+8 in/out digital signals, 2 timers and high precision voltage references temperature compensated. The On-Board Computer - The OBC features:  The On-Board Computer - The OBC features OBC mass is 0.7 kg Power drain of 5 W @ + 5V. The unit can withstand up to 10 Krads Operating temperature range: –20°C to + 60°C. The OBC has a QNX operating system, but full compatibility with other O.S. has been proven in our Labs. All applications SW are written in C++, but we have tested the compatibility with other low-level languages. The On-Board Computer:  The On-Board Computer Mother Board ADC Board SCC Board Mass Memory The On-Board Computer:  The On-Board Computer 130 mm The On-Board Computer – Environmental Testing:  The On-Board Computer – Environmental Testing The OBC has been subjected to radiation and environmental tests (vibration, thermal and thermal-vacuum) with success. The On-Board Computer – Environmental Testing:  The On-Board Computer – Environmental Testing The Hardware during irradiation Radiation withstanding up to 10 Krads The On-Board Computer – Environmental Testing:  The On-Board Computer – Environmental Testing The OBC during vibration test Vibration test performed according to the applicable ECSS-E-10-03A standard (qualification level) The On-Board Computer – Environmental Testing:  The On-Board Computer – Environmental Testing The OBC during Thermal Cycles test 47 Thermal Cycles performed according to the applicable ECSS-E-10-03A standard (qualification level): -20°C to +70°C The On-Board Computer – Environmental Testing:  The On-Board Computer – Environmental Testing The OBC during Thermal Vacuum test Thermal Vacuum tests (8 cycles) performed according to the applicable ECSS-E-10-03A standard (qualification level): -20°C to +70°C The On-Board Computer - Applications:  The On-Board Computer - Applications Besides its use as the core OBC on board nano, micro and minisatellites, we intend to propose the OBC as a navigation computer on launch vehicles and for general computing and TLC/TLM handling purposes for scientific missions both on free-flyers and on the Space Station. The Mass Memory (HDCOTS):  The Mass Memory (HDCOTS) The COTS-based RAID (Redundant Array of Independent Disk Driver) system originated from a market survey showing the absence of makers of spaceborne RAID systems in Europe while such devices have been used on several USA’s space missions. Considering the push from the consumer and professional market towards decreasing prices and the continuous technical evolution of the hard disk technology, it seemed logical to undertake the development of a RAID system looking in prospective to the ever increasing storage capacity of Earth Remote Sensing satellites equipped with optical or radar instruments. The Mass Memory (HDCOTS):  The Mass Memory (HDCOTS) The RAID system consists of a stack of hard disks inclusive of the RAID controller and interfaces with an external computer. The RAID system will be capable of up to 8 pairs of hard disks each with 73 GB capacity (for a total of 1.2 terabytes). A last-generation SCSI interface is adopted to speed up the write/read performance, which is further enhanced by the inherent shared operation of the RAID system. This RAID intends to compete, in terms of cost, mass and power consumption, with the equivalent solid-state products available on the space market. The target applications address mainly the bulk temporary storage of remote sensing images, in the visible, hyper-spectral or radar bands. The Mass Memory (HDCOTS):  The Mass Memory (HDCOTS) The product is under development in the frame of the ASI contract (N. I/030/02/0, as co-funding).  It is an High-Capacity Hard-Disk Memory based on the extensive usage of COTS (Commercial-Off-The-Shelf) - HDCOTS. IMT partners in the development are Alenia Spazio (for the User Reqs definition) and Laben (for Final Testing). Possible applications are space applications in LEO, avionics and military applications. The HDCOTS is composed by 2 counter-rotating Disks in a pressurised box with suitable provisions against vibrations.  Main characteristics Capacity: 146 Gbytes (expandable) Ultra-wide SCSI interface  BUS: 16 Bits  Transfer Speed: about 40 MB/sec  Mass: less than 2.5 Kg ((for the baseline).  Power consumption: in the order of some tens of watts.  Program completion forecast: December 2003 The Mass Memory (HDCOTS) - General Requirements:  The Mass Memory (HDCOTS) - General Requirements Reduced dimensions and mass Reduced costs w.r.t. the Solid State Mass Memories Reduced Power consumption (Extensive usage of COTS Expandable Capacity > 1 TB Transfer Speed > 10-20 MB/sec PC Standard Compatible interface The Mass Memory (HDCOTS)– System Architecture:  The Mass Memory (HDCOTS)– System Architecture The Technological Demonstrator (TD) is a High-Capacity Memory system for space application at low cost. It is composed by memory devices and control electronics in a single box; the power supply can be a separated unit. The Hard Disks are the ideal solution for the implementation of the TD. From space application point of view it implies: - the TD shall be composed by 2 counter-rotating Disks to give a resulting null angular momentum to the satellite during read/write operations; - the TD shall be maintained in a pressurised box such as the internal pressure does not go down to the minimum required by the disk heads since they work on an air cushion. The Mass Memory (HDCOTS) - Architecture:  The Mass Memory (HDCOTS) - Architecture To increase significantly the capacity, modularity and reliability of the memory system, a RAID (Redundant Array of Independent Disk Driver) architecture will be implemented, by using a single control electronics to manage all Disks. Of course, the system will be composed by a multiple of 2 Disks, formed by a pairs of counter-rotating Disks. The TD, as demonstrating model, will be a RAID system reduced to the minimum, formed by a single pair of counter-rotating Disks and a control electronics. The Mass Memory (HDCOTS) - Architecture:  The Mass Memory (HDCOTS) - Architecture As far as the Disks, the SCSI technology has been selected, because the high read/write speed. In addition the significant number of Disks that can be managed will be useful for the development of more complex RAID system. For the TD, Disks with Ultra 160 SCSI interface have been selected, because it is a consolidated standard at low cost w.r.t. the very new Ultra 320. For the Disks we have considered a capacity greater than 40 GB, more than adequate for the current market and applications requirements. The Mass Memory (HDCOTS) - Architecture:  The Mass Memory (HDCOTS) - Architecture The control electronics shall allow the management of the Disks RAID configuration and shall perform interface functions versus the remote computer at similar speed than the transfer speed of the Disks. Such electronics shall be an Ultra 160 SCSI Controller plus a communication interface versus the remote computer. The additional interface shall foreseen a PCI slot, at least, compatible with the controller; in addition an expansion cable versus the remote computer is necessary. The Mass Memory (HDCOTS) - Architecture:  The Mass Memory (HDCOTS) - Architecture The Mass Memory (HDCOTS) – Electrical Design:  The Mass Memory (HDCOTS) – Electrical Design For the interface of the TD and the remote computer the selected solution is from MAGMA, named “PCI Expansion”. The Mass Memory (HDCOTS) – Electrical Design:  The Mass Memory (HDCOTS) – Electrical Design The selected Hard-Disks are: IBM Ultrastar 73LZX Maxtor 73G Ultra 160 SCSI The Mass Memory (HDCOTS) – Electrical Design:  The Mass Memory (HDCOTS) – Electrical Design The SCSI Controller will be selected as results of the evaluation tests performed on the two chosen types. HDCOTS – TD mechanical Design:  HDCOTS – TD mechanical Design HDCOTS – TD mechanical Design:  HDCOTS – TD mechanical Design Slide28:  HDCOTS – TD mechanical Design The Mass Memory (HDCOTS) – EM Test Bench:  The Mass Memory (HDCOTS) – EM Test Bench The Mass Memory (HDCOTS) – EM Test Bench:  The Mass Memory (HDCOTS) – EM Test Bench The Mass Memory (HDCOTS) – EM Preliminary Test:  The Mass Memory (HDCOTS) – EM Preliminary Test The Mass Memory (HDCOTS) – The Electrical Model:  The Mass Memory (HDCOTS) – The Electrical Model PCI expansion SCSI Controller Disk 1 Disk 2 Disk 3 The Mass Memory (HDCOTS) – IBM HD:  The Mass Memory (HDCOTS) – IBM HD The Mass Memory (HDCOTS) – Maxtor HD:  The Mass Memory (HDCOTS) – Maxtor HD The Mass Memory (HDCOTS) – FFD UWSCSI M-Systems:  The Mass Memory (HDCOTS) – FFD UWSCSI M-Systems The Mass Memory (HDCOTS) – SCSI Controller:  The Mass Memory (HDCOTS) – SCSI Controller The Mass Memory (HDCOTS) – PCI Expansion:  The Mass Memory (HDCOTS) – PCI Expansion AIV Plan – Preliminary COTS Verification:  AIV Plan – Preliminary COTS Verification Radiation Test OK Temperature Cycles COTS Selection No Yes OK No Yes Unit Verifications To be performed on Electrical Model To be performed on TD AIV Plan – Electrical Model Verifications:  AIV Plan – Electrical Model Verifications Preliminary Functional Verifications OK Expected performances verifications Electrical Design modification No Yes OK No Yes Radiation Test AIV Plan – Validation Testing:  AIV Plan – Validation Testing Structural Model Vibration Test OK Tests on TD Mechanical Design modification No Yes OK No Yes Vibrations Thermal Cycles -20°C ÷ + 60°C OK No Yes Thermal vacuum -20°C ÷ + 60°C Electrical/ Mechanical Design modification OK No Yes TD validated

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