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Published on October 29, 2007

Author: Carlton

Source: authorstream.com

The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment:  The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment Stefan Ritt Paul Scherrer Institute, Switzerland The MEG Experiment at PSI:  The MEG Experiment at PSI Stopped m beam of 107-108 s-1, 100% duty factor Liquid Xe calorimeter for g detection Solenoidal magnetic spectrometer Radial drift chambers for e+ momentum determination Timing counter for e+ 97 98 99 00 01 02 03 04 05 06 07 Planning R & D Assmbl. Data Taking Goal: m → eg at 10-13 N7-4 T. Iawamoto Waveform Digitizing:  Waveform Digitizing Needed: Pile-up rejection (BG from 108 µ decays in unsegmented calorimeter) ADC dynamic range of 12 bit TDC resolution of 40 ps Analog pipeline (L1 trigger) ~300ns 3000 channels 2 GS 10 Bit 100€/Chn The DRS chip: principle of operation:  The DRS chip: principle of operation Domino Ring Sampler Design of Inverter Chain:  Design of Inverter Chain PMOS > NMOS PMOS < NMOS “Tail Biting”:  “Tail Biting” enable 1 2 3 4 1 2 3 4 Domino Speed Control:  Domino Speed Control UR US UR US Current mode readout:  Current mode readout First implemented in DRS2 (DRS1 had charge readout) Sampled charge does not leave chip Current readout less sensitive to charge injection and cross-talk write read C (200fF) . . . R (700 ) I Vout Vin Timing Reference:  Timing Reference signal 20 MHz Reference clock PMT hit Domino stops after trigger latency 8 inputs shift register Reference clock domino wave MUX Domino speed stability of 10-3 : 400 ps uncertainty for full window 25 ps uncertainty for timing relative to edge The DRS2 Chip:  The DRS2 Chip Fabricated in 0.25 mm 1P5M MMC process (UMC), 5 x 5 mm2 Radiation Hard (CMS Pixel library, R. Horisberger) 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz) Maximal sampling speed 4.5 GHz Readout speed 40 MHz Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004 Packaged chip costs: 35 € / chn. (MPW run) 3 € / chn. (engineering run) Domino Circuit Readout Shift Register 10 channels x 1024 bins DRS2 Test Results:  DRS2 Test Results Preliminary ! Measured DRS2 Parameters:  Measured DRS2 Parameters Linear approximation PLL Stabilization:  PLL Stabilization PLL External Common Reference Clock (1-4 MHz) Vspeed Frequency stabilization:  Frequency stabilization Vspeed 16-bit DAC LUT FPGA Frequency Counter Compensate for temperature drifts Change Vspeed only between events, keep stable during acquisition phase Jitter ~ 150ps Timing accuracy with 9th channel < 25ps 150ps Estimated Bandwidth:  Estimated Bandwidth Input pulse rising time: 0.9 ns Sampled at 2.5 GHz: 0.4 ns / sample Reconstructed rise time: 3 samples → 1.2 ns Estimated BW » 500 MHz Limited by protection diodes 40 MHz readout clock Direct DRS2 output DAQ Boards:  DAQ Boards DRS R. Paoletti, N. Turini, R. Pegna MAGIC collaboration USB PSI GVME Board FPGA with 4 Power-PC Digitized Signals:  Digitized Signals 7 ns pulses 500 mV Digitized at 2.5 GHz with USB test board Signal-to-noise ratio:  Signal-to-noise ratio mV mV 1 V DC input signal, common mode subtracted Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit) Integration over 100 ns PMT pulse (250 bins) has RMS of 0.16 mV → SNR = 6200:1 (12.6 bit) Could be improved by better analog design of Mezzanine board Waveform Analysis:  Waveform Analysis MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec Compress “interesting” and pile-up events in FPGA (→ 10x) Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data Overall data rate ~2 MB/sec pb Experiment 500 MHz sampling Next generation: DRS3:  Next generation: DRS3 ? Conclusions:  Conclusions Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz Deploy ~200 channels in MEG Experiment in spring 2005 Use DRS2 for drift chamber readout Final version (DRS3, 3000 channels) in 2006 Not specific to MEG, useful for other experiments

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