Risc

50 %
50 %
Information about Risc
Education

Published on April 26, 2014

Author: shilpaitft

Source: slideshare.net

Description

RISC/CISC Architecture

RISC / CISC Architecture.

Overview • CISC Architecture • RISC Architecture • Pipelining • RISC vs CISC

What is CISC • Complex Instruction Set Computer • “High level” Instruction Set • Executes several “low level operations” • Ex: load, arithmetic operation, memory store

Features of CISC • Instructions can operate directly on memory • Small number of general purpose registers • Instructions take multiple clocks to execute • Few lines of code per operation

What is RISC? • Reduced Instruction Set Computer • RISC is a CPU design that recognizes only a limited number of instructions • Simple instructions • Instructions are executed quickly

Features of RISC  “Reduced” instruction set  Executes a series of simple instruction instead of a complex instruction • Instructions are executed within one clock cycle • Incorporates a large number of general registers for arithmetic operations to avoid storing variables on a stack in memory • Only the load and store instructions operate directly onto memory • Pipelining = speed

Pipelining • “Assembly Line” • Technique to process multiple instructions at the same time • Allows instructions to be executed efficiently

Stages of Pipelining • Fetch instructions from memory • Decode the instruction • Execute the instruction or calculate an address • Access an operand in data memory • Write the result into a register

Pipelining Example

CISC vs RISC CISC RISC Complex instructions require multiple cycles Reduced instructions take 1 cycle Many instructions can reference memory Only Load and Store instructions can reference memory Instructions are executed one at a time Uses pipelining to execute instructions Few general registers Many general registers

Add a comment

Related presentations

Related pages

Reduced Instruction Set Computer – Wikipedia

Reduced Instruction Set Computer (RISC, englisch für Rechner mit reduziertem Befehlssatz) ist eine Designphilosophie für Computerprozessoren. Der Begriff ...
Read more

Reduced instruction set computing - Wikipedia, the free ...

Reduced instruction set computing, or RISC (pronounced 'risk'), is a CPU design strategy based on the insight that a simplified instruction set (as opposed ...
Read more

CISC und RISC - Die Gegensätze der Rechnerarchitekturen.

CISC und RISC - Die Gegensätze der Rechnerarchitekturen Was bedeuten die Abkürzungen? RISC und CISC stehen für die Begriffe Reduced Instruction Set ...
Read more

RNA-induced silencing complex – Wikipedia

Der RNA-induced silencing complex (RISC) ist ein Komplex aus RNA und Proteinen. Bei der RNA handelt es sich um eine small interfering RNA (siRNA) oder ...
Read more

RiSc GmbH | Die RiSc GmbH ist Ihr professioneller ...

Die RiSc GmbH ist Ihr professioneller Personaldienstleister im Bereich Bühnen- und Messebau.
Read more

risc-os.de: RISC OS Screenshots

RISC OS 5.17 BeagleBoard-xM Desktop mit OvationPro, 1280 x 720, Raik Fischer RISC OS 5.17 BeagleBoard-xM Desktop mit CDVDBurn, DPingScan und PhotoDesk ...
Read more

RISC und CISC - Bernd Leitenbergers Info Site

RISC und CISC. In meiner kleinen Reihe über Rechnerarchitekturen wurde schon beschrieben, wie man mit Pipelines die Durchlaufzeiten eines Befehls ...
Read more

R.I.S.C.: Home

Willkommen in der R.I.S.C.-Gefahrstoff-Datenbank. R.I.S.C. steht für RisikoInformation SchulChemikalien. Informationen über Sicherheitsmerkmale und ...
Read more

What is RISC? - Stanford Computer Science

RISC? RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions ...
Read more

RiscPC - Wikipedia, the free encyclopedia

The RiscPC (stylised with a half-space [4] [self-published source?] as Risc PC, also referred to as Risc PC and codenamed Medusa) was Acorn Computers's ...
Read more