Research & Development

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Information about Research & Development

Published on June 15, 2007

Author: CoolDude26



Research & Development on SOI Pixel Detector :  Research andamp; Development on SOI Pixel Detector H. Niemiec, T. Klatka, M. Koziel, W. Kucewicz, S. Kuta, W. Machowski, M. Sapor, M. Szelezniak AGH – University of Science and Technology, Krakow K. Domanski, P. Grabiec, M. Grodner, B. Jaroszewicz, A. Kociubinski, K. Kucharski, J. Marczewski, D. Tomaszewski Institute of Electron Technology, Warszawa M. Caccia University of Insubria, Como Presented by Halina Niemiec Outline:  Outline Short introduction to the SOI sensor Applications of the SOI sensors Preliminary test of the small area SOI sensors on the high resistive substrates Design of the full size SOI sensor The SOI project is partially supported by the G1RD-CT-2001-000561 Introduction :  Introduction The idea: Integration of the pixel detector and readout electronics in the wafer-bonded SOI substrate Detector  handle wafer High resistive (andgt; 4 kcm,FZ) 300 m thick Conventional p+-n DC-coupled Electronics  active layer Low resistive (9-13 cm, CZ) 1.5 m thick Standard CMOS technology Applications of the SOI detectors:  Applications of the SOI detectors SOI detectors: High charge signals corresponding to minimum ionising particles (about 22000 e+e-), fully depleted Attractive solutions for low energy radiation detection Monolithic, flexibility of the readout electronics design (NMOS and PMOS in readout channel) Possible option for vertex detectors One of possible applications: Beam monitor in hadrontherapy System basing on secondary electrons emission from a thin aluminium foil. Kinetic energy of electrons = 20 keV  particle range in silicon = 3 m Detection of such electrons is possible in SOI detector without any backthinning process. Beam monitor Test structures of the SOI detector:  Test structures of the SOI detector Small readout matrices (8x8) with associated detector diodes or input pads for external signal sources were fabricated on the SOI wafers at the IET, Warsaw Two readout channel configurations – with NMOS transistor switch (cell dimensions 140x122 m2) and with transmission gate (140x140 m2) Contact to the detector placed in the V-shape cavity. Row selection signals led by two parallel lines with opposite polarization, body of the structure densely grounded  reduction of the cross-talk between the electronics and detector, circuit protection against radiation induced latch-up. Characterization of readout channels:  Dynamic range: 0.3 MIP  300 MIP (2-MOS switch) 0.3 MIP  150 MIP (1-MOS switch) Output r.m.s. noise: 270 V ENC: 990 e- Cross-talk between neighbouring channels: andlt; 0.1 % Characterization of readout channels Transfer characteristics were measured with external voltage pulse signal, assuming that the charge to voltage conversion ratio for the SOI detector is about 6 mV/MIP. The circuit is optimised for the applications where high particle fluxes are expected Preliminary tests of sensor matrices:  Preliminary tests of sensor matrices Tinteg=2 ms Tinteg=1 ms Strontium 90 beta source – recorded events in the detector Source placed on the top of the detector Detector polarization: Vdet = 60 V, different integration times „Steps' on the output waveforms indicate detected particles Matrices with one-transistor switches were chosen for the tests of the complete sensor. Matrix dimensions: 1120 m 976 m Estimation of the leakage currents:  Estimation of the leakage currents Indirect method of the leakage current measurements - the output signals corresponding to the integrated leakage current measured for the detector polarization up to the 100V For the integration time of 500 s and charge to voltage conversion ratio of 6mV/MIP: Ileakage 400 nA/cm2 Full depletion at about 60 V The value of the leakage current determined by the quality of the SOI substrate – similar results obtained for the detector produced on the SOI wafers with etched-down upper Silicon layer (no electronic device produced) Calibration of the SOI sensor:  Calibration of the SOI sensor Radioactive source: Sr90 beta source Integration time: Tint = 500 s Detector polarization: Vdet= 60 V 5.9 mV/MIP Pedestal value =69.9 mV ; pedestal width = 21.1 mV First signal peak= 75.8 mV; signal peak width = 21.8 mV Preliminary tests with the laser light:  Preliminary tests with the laser light Laser light not focused, shining from the backplane (biased by metal mash) Wavelength = 850 nm 4 s wide light pulses - each corresponding to 3.4 MIP Integration time = 1 ms Detector polarization=60V 10 000 events recorded Good detector sensitivity for the ionising radiation and linear response as a function of the generated charge was observed. Design of a full size sensor:  Design of a full size sensor Detector layout: Dimensions: 24x24 mm2 128 x 128 = 16 384 channels 4 subsegments with independent parallel analogue outputs Cell dimensions: 160x160m2 Possibility to extend to ladders with dimensions up to 72x24 mm2 and small dead areas Detector readout: Exercised on the prototype chip designed in commercial AMS 0.8 technology Analogue serial readout organisation Compatible with external CDS Well defined integration time and short dead time Summary:  Summary A solution of the monolithic pixel detector realized in SOI technology was proposed and first small area test structures of the detectors have been fabricated. Preliminary tests with laser light and radioactive source were performed and indicated high detector sensitivity for the ionising radiation. Further measurements with the usage of dedicated DAQ will start nearest days. Detailed tests with a focused laser spot will be carried-on nearest weeks and allow to study charge generation and sharing mechanisms for the new sensor. Next steps of the sensor development will be design of the fully functional and large area SOI sensors. In this chip the readout scheme exercised with the prototype front-end electronics designed in commercial technology will be implemented. The fabrication of the sensor will be completed next year.

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