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Published on October 30, 2007

Author: Mee12

Source: authorstream.com

Coincidence Matrix ASIC prototype performances :  Coincidence Matrix ASIC prototype performances CMA PRR CERN, 15 December 2003 Level-1 barrel muon trigger scheme:  Level-1 barrel muon trigger scheme Inner and outer RPC signals have to be fan-out with a splitter logic. Pivot and inner RPC signals coming from the splitter boxes go to four Coincidence Matrix ASICs, mounted on a low pT PAD box. Trigger signals coming out from the low pT PAD logic and the RPC3 signals coming from the splitter go to the high pT PAD box. High pT PAD output signals (serial optical link) are collected by the off-detector receiver boards, which contains the Sector Logic. The RX sends trigger data to the MUCTPI and readout data to the Read Out Driver. CMA functionality:  CMA functionality The Coincidence Matrix ASIC performs most of the functions needed for the low-pT and high-pT triggers and for the read-out of the ATLAS Barrel Level1 Muon Trigger Trigger and readout of 192 RPC FE signals Timing and digital shaping of the signals coming from the RPC doublets Execution of the trigger algorithm, local muon track candidates identification and pT classification ROI overlap flagging Data storage during Level1 latency Storage of readout data in derandomizing memory RPC hit time measurement with 3.125 LSB (1/8 BC) Readout data serializer CMA architecture:  CMA architecture CM ASIC history:  CM ASIC history CM ASIC submitted 20th November 2001 49 dies packaged by March 15th 2002 (wrong bonding) Industry testboard arrived 10th March to Milano test site Industry tests started 21st March on 49 packages 7th April functional tests sent by Rome to industry 20th April RAM test vectors sent by Rome to industry 29th April 44 fully tested package devices at Microtech 23rd May 37 devices with new package tested at Microtech 15th June 2002 CMA in Rome CMA layout:  CMA layout UMC 0.18 mm, 6 metal layers, 1.8 V core power supply, 3.3 V I/O pads 430 kgates Chip area: 22 mm2 Virtual Silicon standard cell library 320 MHz PLL (x8) macro 24 double-port RAMs 352 pins BGA package CMA test board:  CMA test board Loadboard developped for Teradyne tester, has been designed with additional connectors for PLL test and lab tests in Rome. Test patterns:  Test patterns Scan and functional tests were performed on Teradyne machine at 1 Mhz, 40 Mhz, at room and at 125C temperatures. PLL lock was also tested. SCAN tests: 32 scan chains, maximum of 900 cells, generated with Synopsys Test Compiler. RAM tests: using single dedicated scan chain (23,743,440 cycles), generated from RTL model and converted to compressed ATP format. Functional tests 105576 vectors, to test I2C interface and start PLL, generated from full netlist+timing simulation, converted to ATP format. Industry test results:  Industry test results 49 0208 packages tested: 7 failing on GND 1 RAM fail 1 SCAN fail 40 OK (81.6% yield) 37 1219 packages tested: No GND fails (already discarded?) 4 RAM fails 3 SCAN fails 30 OK (81.1% yield) 70 ASICs good, to be used for further tests and irradiation. LAB setup:  LAB setup 36x64K T=6.125ns Pattern generator Clock jitter Waveform Analyser T=10ns Generator PODs GPIB LAN loadboard I2C on RJ45 Rome lab test:  Rome lab test LAB setup with limited capability has been used to do preliminary tests. I2C on parallel port interface and C++ linux application has been used to initialize ASIC. PLL test: 160 MHz derived clock output has been used to check PLL stability (320 MHz) PLL has been characterized vs V and vs input frequency PLL is working according to specifications PLL 160 MHz clock test:  PLL 160 MHz clock test Trigger test:  Trigger test Trigger test on a limited number of input channels, due to limitations on the laboratory setup: Minimum pulse width measurement Twmin > 6.126 ns (12 ns in specs) Dead timer, pulse shaping and pipeline delay working according to specs. Input to K-pattern delay: Tlatkpat = 59 ± 1 ns Input to THReshold/OVerLap delay: Tlatthr = 63÷88 ± 1 ns Skew between THR and OVL signals: Toutskew = 2 ± 0.5 ns Readout tests:  Readout tests Readout link is a two-wire Dslink protocol working at 80-40-20-10-5-2.5-1.125 Mbit/s Readout tests done at 40 Mbit/s using: 10ns period sampling with waveform analyser GPIB LAN box connected to waveform analyser CMID L1ID … BCID + 16-bit hits … 8-bitCRC Readout tests:  Readout tests VISA-GPIB library (linux) in deserializer program has been used to convert waveform vectors to readout data fragments. c151 -- CMID 0 FEL1ID 337 87d8 -- FEBCID 2008 0700 -- BC 0 TIME 7 IJK 0 STRIP 0 0745 -- BC 0 TIME 7 IJK 2 STRIP 5 0685 -- BC 0 TIME 6 IJK 4 STRIP 5 07c0 -- BC 0 TIME 7 IJK 6 STRIP 0 07e3 -- BC 0 TIME 7 OVL 0 THR 3 4075 -- CRC 75 Time interpolator linearity:  Time interpolator linearity Hits on four channels have been generated, in 1 ns steps, within a range of 4 BCs (CH 1-4), also trigger output time is measured (K). Very preliminary Readout latency:  Readout latency Max LVL1 input frequency. 1% RPC occupancy 1-BC window Power consumption:  Power consumption Core nominal power consumption: 1.26 W Estimated values from worst case corner (Synopsys) was 1.3 W. Level-1 slice lab test:  Level-1 slice lab test CM initialization working correctly. L1A sent from TTCvi at maximum readout frequency to check PAD frame integrity. Time alignment for all CM signals coming from PRODE (CLK, L1A, BCR, ECR), in order to have all CM counters synchronous and aligned. Test repeated with hit pattern generator (four CMs on low pT PAD). System working for days without errors. PAD Box:  PAD Box CMA eta CMA phi PAD logic Programmable Delay ASICs ELMB TTCrx Optical link tx H8 muon beam slice test:  H8 muon beam slice test Summer 2003 2 BML, 2 BOL chambers 3 RPC stations 1 low pT PAD with 2 CMAs 1 high pT PAD with 2 CMAs H8 CMA test:  H8 CMA test First ASIC beam test with all 2x32+2x64 inputs from FE Initialization: serial interface working correctly, noise on PAD mother board. Trigger: Input signals masking logic Pipeline depth for FE signals timing adjustment Input and output signal shaping De-clustering logic Majority logic (2/4, 3/4 and 4/4) Overlap logic Trigger roads Readout logic: Readout window (latency time and window depth) BC capability CM ASIC working as expected Data analysis still ongoing (some problems on event synchronization). RPC efficiency (25 ns run):  RPC efficiency (25 ns run) Chamber efficiency with CM readout vs strip number using MDT data RPC hit map for inner and outer chambers (TDC beam profile in blue) Trigger efficiency (25 ns run):  Trigger efficiency (25 ns run) Low pT trigger eta projection efficiency vs strip number on pivot plane using MDT reconstructed tracks RPC trigger BC capability (25 ns run):  RPC trigger BC capability (25 ns run) Readout system time resolution: s=1.9 ns hit arrival time difference between CM (3 ns LSB) and TDC (1.015 ns LSB) Low pT trigger bunch counter identification efficiency vs pipeline delay CM ASIC uses 1/8 BC LSB time interpolator to measure time of arrival of RPC hits and trigger output Radiation test:  Radiation test TID: 300 Gy NIEL: 2.4E12 n/cm2 (1 MeV eq.) SEU: 3.0E11 p/cm2 SEUf = (soft SEUm / ARL) · (SRLsee / 10y) · Sfsim 60 MeV proton test, June 2003, Louvain-la-Neuve: Industry test board used on the beam After initialization all internal registers values were monitored to check SEUs (re-initialization in case of SEU) via I2C Current consumption was continuously monitored SEU output signal was checked Results: No latchup was observed, no current increase SEUs were detected on registers, but no SEU signal assertion on threshold registers. Foreseen soft SEU rate:  Foreseen soft SEU rate ------------------------------------------------------------ run 4 ------------------------------------------------------------ fluence = 3.6e11 cm-2 SRLsee = 6.0e9 h>20MeV /cm2 irradiation time = 927 sec SEU detected: 115 No. bits tested per CMA = 1866 No. bits to be considered for SEU = 2072 (168 bits from redundant registers) ------------------------------------------------------------ seu rate foreseen per chip = 1.06e-07 SEU/sec seu rate foreseen per bit = 5.14e-11 SEU/sec ------------------------------------------------------------ cross section per bit = 1.71e-2 cm2 ------------------------------------------------------------ seu rate foreseen for the redundant registers (56 bits) = 1.48e-19 SEU/sec seu rate foreseen for the redundant registers for 4000 chip = 1.53e-09 SEU/mese ------------------------------------------------------------ seu rate foreseen for the others registers for 4000 chip = 4.26e-4 SEU/sec = 36.78 SEU/day ------------------------------------------------------------ Conclusions:  Conclusions Waiting for the H8 data study The ASIC showed a correct functionality A few modifications have to be implemented

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