Published on February 25, 2014
Imagination Unveils MIPS Series 5 Warrior MClass MCU IP Cores The folks from Imagination are currently attracting attention at both Embedded World and the Mobile World Congress. In particular, they are introducing their Warrior MClass family of cores in the form of the MIPS M51xx, which they describe as the first MCU IP cores with hardware virtualization. Block diagrams for the MIPS M5100 and M5150 are shown below. In addition to a single/double precision FPU (floating-point unit), each of these MCUs boasts a hardware virtualization MMU (memory management unit). 
 A five-stage pipeline provides maximum performance at minimum frequency with 1.57 DMIPS/MHz and 3.4 Coremark/MHz. The DSP and SIMD (single instruction, multiple data) engine has 150 dedicated instructions, including 70 x 128-bit SIMD instructions. Meanwhile, reduced interrupt latency is advantageous for real-time operations. Security and reliability are becoming "must haves" in today's embedded systems. A traditional non-virtualized system typically features a single operating system with virtual memory, which means that user applications can be protected from each other. By comparison, in the case of a virtualized system, the root of the system is a secure hypervisor/kernel. In addition to protecting applications, such a system also protects multiple operating systems from tampering with each other.
 The MIPS M5100 offers "virtualization lite" in the form of root/guest FMTs, while the M5150 provides full virtualization using root/guest TLM MMU. This scalable system supports up to seven "guests" in the form of concurrently running operating systems and/or applications. The benefits of this system include ease-of-use (no modification is required to a guest OS), reliability (corruption or crashing of one OS cannot affect another), and optimal performance that is facilitated by intelligent resource allocation. Additional security is provided by a suite of anti-tamper features, including hardware security (user-defined scrambling of cache RAM and SPRAM data and addresses), timing and power analysis countermeasures (injection of random pipeline stalls), and two pseudo-random number generators for use by the core logic and application software. For more information on these and other MIPS cores, please visit the Imagination Website. — Max Maxfield, Editor of All Things Fun & Interesting Related posts: 1. http://www.eetimes.com/document.asp?doc_id=1321147&image_number=1 2. http://www.eetimes.com/document.asp?doc_id=1321147&image_number=2
3. http://www.eetimes.com/document.asp?doc_id=1321147&image_number=3 4. http://www.imgtec.com/mips/mips-processor.asp
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