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Information about mbarrel062002

Published on October 31, 2007

Author: Felipe


CMA LVL1 Barrel status:  CMA LVL1 Barrel status ATLAS TDAQ week July 2003 History:  History CMA ASIC submitted 20th November 2001 49 dies packaged by March 15th with four-pin bonding following preliminary specs (package 0208). New wafers had to selected for packaging with final Bonding. Loadboard arrived 10th March to test site (Milano), following specifications (package 0219), had to be fixed to package 0208. Industry tests started 21st March on 49 packages 0208 with scan tests. History 2:  History 2 7th April functional tests sent by Rome to industry 15th April 5 0208 tested devices (no RAM tests) and loadboard sent to Rome. 20th April RAM test vectors sent by Rome to industry. 29th April 44 fully tested 0208 package devices at Microtech. 23rd May 37 devices with package 0219 tested at Microtech. CM ASIC layout and architecture:  CM ASIC layout and architecture 430 kgates UMC 0.18 mm, 320 MHz PLL (X8), 24 double-port RAMs. CMA ASIC pinout:  CMA ASIC pinout Package 0208 and 0219 differ only on the position of PLL signals and supplies. Both of them are working correctly CMA Loadboard:  CMA Loadboard Loadboard developped for Teradyne tester, has been designed with additional connectors for PLL test and lab tests in Rome. Test patterns:  Test patterns Scan and functional tests were performed on Teradyne machine at 1 Mhz, 40 Mhz, at room and at 125C temperatures. PLL lock was also tested. SCAN tests: 32 scan chains, maximum of 900 cells, generated with Synopsys Test Compiler. RAM tests: using single dedicated scan chain (23,743,440 cycles), generated from RTL model adn converted to compressed ATP format. Functional tests 105576 vectors, to test I2C interface and start PLL, generated from full netlist+timing simulation, converted to ATP format. Industrial test results:  Industrial test results 49 0208 packages tested: 7 failing on GND 1 RAM fail 1 SCAN fail 40 OK (81.6% yield) 37 1219 packages tested: No GND fails (already discarded?) 4 RAM fails 3 SCAN fails 30 OK (81.1% yield) 70 ASICs good, to be used for further tests and irradiation. LAB setup:  LAB setup 36x64K T=6.125ns Pattern generator Clock jitter Waveform Analyser T=10ns Generator PODs GPIB LAN loadboard I2C on RJ45 Tests done in Rome:  Tests done in Rome LAB setup with limited capability has been used to do preliminary tests. I2C on parallel port interface and C++ linux application has been used to initialize ASIC on all tests shown here. Four CM ASICs mounted on CM boards will be used for further tests. PLL tests:  PLL tests 160 MHz derived clock output has been used to check PLL stability (320 MHz) 40 MHz input 160 MHz on dedicated IO PLL tests 2:  PLL tests 2 PLL has been characterized vs V and vs input Frequency. PLL is working to specifications PLL vs Voltage:  PLL vs Voltage PLL vs frequency:  PLL vs frequency Trigger tests:  Trigger tests Trigger tests have been done so far on a limited number of input channels, due to limitations on the laboratory setup. Minimum pulse width measurement Twmin > 6.126 ns (12 ns in specs) Dead timer, pulse shaping and pipeline delay working according to specs. Trigger output latency:  Trigger output latency Input to K-pattern delay Tlatkpat = 59 +- 1 ns Input to THReshold/OVerLap delay Tlatthr = 63-88 +-1 ns Skew between THR and OVL signals Toutskew = 2 +- 0.5 ns. Readout tests:  Readout tests Readout link is a two-wire Dslink protocol working at 80-40-20-10-5-2.5-1.125 Mbit/s Readout tests done at 40 Mbit/s using: 10ns period sampling with waveform analyser GPIB LAN box connected to waveform analyser CMID L1ID … BCID + 16-bit hits … 8-bitCRC Readout tests 2:  Readout tests 2 VISA-GPIB library (linux) in deserializer program has been used to convert waveform vectors to readout data fragments. c151 -- CMID 0 FEL1ID 337 87d8 -- FEBCID 2008 0700 -- BC 0 TIME 7 IJK 0 STRIP 0 0745 -- BC 0 TIME 7 IJK 2 STRIP 5 0685 -- BC 0 TIME 6 IJK 4 STRIP 5 07c0 -- BC 0 TIME 7 IJK 6 STRIP 0 07e3 -- BC 0 TIME 7 OVL 0 THR 3 4075 -- CRC 75 Time interpolator linearity:  Time interpolator linearity Hits on four channels have been generated, in 1 ns steps, within a range of 4 BCs (CH 1-4), also trigger output time is measured (K). Very preliminary Readout latency:  Readout latency Max LVL1 input frequency. 1% RPC occupancy 1-BC window Power vs voltage:  Power vs voltage Power vs frequency:  Power vs frequency CM board Eta:  CM board Eta PCBs to be mounted on PAD prototype are ready RJ45 (from splitters) PAD Motherboard connections LVDS receivers CMA CM board Phi:  CM board Phi Four ASICs mounted on two eta and two phi boards by June 21st. FE receivers RN connectors (from wired-OR) CMA

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