Lecture24 Multiprocessor

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Information about Lecture24 Multiprocessor

Published on March 14, 2008

Author: allankliu

Source: slideshare.net


Courseware for Multiprocessor

Comparisons on OS Extension/Customization Multiprocessor OS Approaches Exokernel Downloading code into the kernel The graybox approach OS configuration Virtual machine CS 256/456 Comparison on flexibility Dept. of Computer Science, University of Rochester how much changes in the original OS? overall simplicity overhead of each customization/extension 4/18/2005 CSC 256/456 - Spring 2005 1 4/18/2005 CSC 256/456 - Spring 2005 2 Multiprocessor Hardware Multiprocessor Applications A computer system in which two or more CPUs share full access to the main memory Multiprogramming Each CPU might have its own cache and the coherence Multiple regular applications running concurrently among multiple cache is maintained Write operation by a CPU is visible to all other CPUs Concurrent servers writes to the same location is seen in the same order by all Web servers, … … CPUs (also called write serialization) Parallel programs CPU CPU CPU Utilizing multiple processors to complete one task ……… Cache Cache Cache Strong synchronization Memory 4/18/2005 CSC 256/456 - Spring 2005 3 4/18/2005 CSC 256/456 - Spring 2005 4

Single-processor OS vs. Multi-processor OS Multiprocessor OS Single-processor OS easier to support kernel synchronization – why? easier to perform scheduling – less complex. Multi-processor OS OS structure synchronization Bus scheduling Each CPU has its own operating system quick to port from a single-processor OS Disadvantages difficult to share things (processing cycles, memory, buffer cache) 4/18/2005 CSC 256/456 - Spring 2005 5 4/18/2005 CSC 256/456 - Spring 2005 6 Multiprocessor OS – Master/Slave Multiprocessor OS – Shared OS Bus Bus All operating system functionality goes to one CPU no multiprocessor concurrency in the kernel All CPUs run a single OS instance Disadvantage The OS itself must handle multiprocessor synchronization OS CPU consumption may be large so the OS CPU becomes have a big kernel lock – only one processor can execute in the the bottleneck (especially in a machine with many CPUs) kernel at a time support fine-grain synchronization 4/18/2005 CSC 256/456 - Spring 2005 7 4/18/2005 CSC 256/456 - Spring 2005 8

Multiprocessor Kernel Synchronization TSL on Multiprocessor Protecting short critical region – busy waiting is OK Disabling interrupts does not work Software spin locks Hardware spin locks using TSL entry_section: TSL R1, LOCK | copy lock to R1 and set lock to 1 CMP R1, #0 | was lock zero? JNE entry_section | if it wasn’t zero, lock was set, so loop RET | return; critical section entered exit_section: On multiprocessor, the TSL implementation is more complex, usually MOV LOCK, #0 | store 0 into lock it has to lock the memory bus RET | return; out of critical section 4/18/2005 CSC 256/456 - Spring 2005 9 4/18/2005 CSC 256/456 - Spring 2005 10 More on TSL Locks Spin or Yield? Every TSL is a read/write, image multiple CPUs are busy Multi-processor synchronization. waiting on one block, there will be a lot of traffic on the bus A process is waiting for an event, triggered by another process. CPU CPU CPU ……… Spinning wastes CPU cycles Cache Cache Cache Switching also uses up CPU cycles Should it spin wait or yield the processor? Memory Precede each TSL lock will a trylock (basically a simple read) only when trylock shows the lock is not locked, a TSL lock will be applied 4/18/2005 CSC 256/456 - Spring 2005 11 4/18/2005 CSC 256/456 - Spring 2005 12

Multiprocessor Scheduling Disclaimer Timesharing using a single wait queue (protected by synchronization) Parts of the lecture slides contain original work by for scheduling Andrew S. Tanenbaum. The slides are intended for the sole purpose of instruction of operating systems at the University of Rochester. All copyrighted materials cache affinity belong to their original owner(s). affinity-based scheduling synchronization of parallel programs gang scheduling 4/18/2005 CSC 256/456 - Spring 2005 13 4/18/2005 CSC 256/456 - Spring 2005 14

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