Published on March 8, 2014
IEW International Electrostatic Discharge Workshop The International ESD Workshop will host its 8th edition in 2014 and will be held for the first time in the breathtaking setting of the French Alps. This great event is characterized by a friendly, interactive atmosphere and provides a wonderful environment for envisioning, developing, and sharing ESD design and test technology for present and future semiconductor applications. Special focus topics for the 2014 IEW include “Automotive EOS/ ESD” and “Foundry Support and CAD for ESD”, but a number of other key topics (such as technology innovation in the ESD field, System-Level ESD events, EOS, ESD test methods) will also be featured and discussed. Experience the unique interactive program of the IEW Workshop. • • • • • Listen to experts Share your ideas Give your inputs Ask questions Network with high-level ESD experts from industry Learn in an informal, interactive, and constructive atmosphere. A highly rewarding experience! May 19-22, 2014 Grand Hôtel de Paris, Villard de Lans, France EOS/ESD Association Inc. 7900 Turin Rd., Bldg. 3 Rome, NY 13440-2069, USA PH +1-315-339-6937 • Fax +1-315-339-6793 Email: email@example.com • www.esda.org
Management Committee: Management Committee Chair: Alan Righter, Analog Devices Technical Program Chair: Lorenzo Cerati, STMicroelectronics Program, Registration, and Publications Chair: Pascal Salome, Serma Technologies Seminar Chair: Markus Mergens, QPX Invited Speaker Chair: Dimitri Linten, imec Discussion Groups Chair: Matthew Hogan, Mentor Graphics Keynote Speaker Chair: Harald Gossner, Intel Mobile Communications Special Interest Groups Chair: Wolfgang Stadler, Intel Mobile Communications Audio/Visual Chairs: Alexandre Dray, STMicroelectronics Michael Mayerhofer, Infineon Technologies Publicity Chair: Bart Keppens, Sofics US: James W. Miller, Freescale Semiconductor Europe: Harald Gossner, Intel Mobile Communications Dimitri Linten, imec Philippe Galy, STMicroelectronics Asia: Joshua Yoo, Core Insight US University: Juin J. Liou, University of Central Florida Europe University: Marise Bafleur, LAAS Asia University: Steve Voldman, Dr. Steven H. Voldman, LLC Industry Council Advisor: Charvaka Duvvury ESDA IEW Business Unit Manager: Alan Righter, Analog Devices ESDA HQ Director of Operations: Lisa Pimpinella ESDA Education Business Unit Manager: Ginger Hansel, Dangelmayer Associates Technical Program Committee Gianluca Boselli, Texas Instruments Victor Cao, GlobalFoundries Yiqun Cao, Infineon Technologies Michael Chaine, Micron Technology Leonardo Di Biccari, STMicroelectronics James Di Sarro, IBM Kai Esmark, Infineon Technologies Evan Grund, Grund Technical Solutions Michael Khazhinsky, Silicon Labs Hans Kunz, Texas Instruments Timothy Maloney, Intel Mototsugu Okushima, Renesas Dionyz Pogany, University Vienna Akram Salman, Texas Instruments Theo Smedes, NXP Semiconductors Howard Tang, UMC David Tremouilles, LAAS-CNRS Johan Van der Borght, Sofics Vladislav Vashchenko, Maxim Integrated Products Heinrich Wolf, Fraunhofer IZM Eugene Worley, Qualcomm 2
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Keynote This year’s IEW will present a keynote speaker from one of the world’s leading institutions for particle physics, the European Organization for Nuclear Research (CERN), located two hours north of Grenoble at the border between France and Switzerland. The recent discovery of the Higgs-Boson at CERN’s Large Hadron Collider (LHC) resulted in the 2013 Nobel Prize in Physics for the theoretical physicists predicting this particle which can explain the mass of all matter. However, this would not have been possible without the extensive use of silicon devices in the huge detectors. They analyze the particle reaction making use of the particular interaction of high energy particles with semiconductors. It is our pleasure to welcome a speaker from the detector experiment ‘Compact Muon Solenoid’ (CMS) giving us insight into this exciting field. Keynote Compact Muon Solenoid (CMS) Dr Marcello Mannelli, Senior Research Physicist at CERN-PH Department Abstract: The CMS apparatus at the LHC collider (CERN, Geneva, Switzerland) investigates particle physics phenomena at the high-energy frontier. The discovery of a Higgs-Boson in 2012 is one of the highlights in a wealth of results obtained from precision measurements of known particles and searches for the yet unknown. CMS uses 200 m² of monocrystalline silicon diode detectors segmented in strips and 66 million channels of silicon diode detectors readout in small pixels to measure precisely the tracks of about one thousand particles originating in proton-proton collisions every 25 nanoseconds. An overview of the experiment’s physics goals and of these detectors will be given. 4 Presenter Biography: Dr Marcello Mannelli received a PhD in Elementary Particle Physics from Yale University in 1998. In the summer of that year he came to CERN to work on the OPAL experiment at LEP. Over the next decade he contributed to the searches for the Higgs Boson, and played a leading role in the precision Electro-Weak physics program at LEP. Since 1996 his focus has been on the CMS experiment at the LHC. Here he was a leading proponent of the innovative all-silicon tracker for the CMS experiment, and then went on to hold a number of project responsibilities for the construction and commissioning of the CMS Tracker. Since the start of LHC operation, he has participated in the analysis effort leading to the discovery of the Higgs Boson in the summer of 2012, and its subsequent characterization. At the same time, he is also involved in the preparation of the program of upgrades to the CMS experiment, aimed at making effective use of the substantial increase in the capabilities of the LHC accelerator, foreseen for the early 2020’s.
Invited Talks Invited Talk 1 Invited Talk 2 Abstract: In 3D IC technology thinned chips are stacked and interconnected using through Si vias (TSVs) and micro-bumps. This technology brings new reliability challenges. The failure mechanisms are not mainly caused by electrical stress, as was the case for conventional ICs, but thermal, mechanical and thermo-mechanical issues play an increasing role. This not only demands for a screening of processing and material choices, but also for new functional, reliability and failure analysis test methods and methodologies. In this talk, an overview of reliability challenges for the 3D IC via-first technology will be given. This includes Cu-TSV related problems such as barrier and liner integrity, electromigration and Cu pumping, TSV impact on back-end- and front-end-of-line reliability and devices, keep-outzones, ESD, chip thinning and stacking related issues, microbump reliability, and chip-package interaction (CPI). Abstract: Most of the IC design houses do not have their own Fab to produce the integrated circuits and so they have to choose a foundry partner who provides technology data as well as libraries, simulation & verification files and documentation. The amount of offered material varies depending on foundry and technology, in some cases the information is limited, especially for the new technologies. Not knowing each detail of the technology requires additional support by the foundry experts in particular when doing HV designs. This support is a key factor for a successful project, and finally it is a win-win situation for both customer and foundry once the product is on the road. To provide a support flow from the very beginning of a project till qualification is a must for analogue HV mixed mode circuits at least for automotive products. This flow should include a review of the system the IC is built in, an ESD/HV concept definition including a pre selection of the IO cells, proposal of mandatory documents the customer should use and simulation/verification hints. Depending on the foundry services also backend support as assembly, testing, ESD/LU testing and qualification is provided. Based on the type of project the required assistance might differ. A research company will be in need of other support than a design house developing a product for a particular solution. 3D IC Reliability Challenges: New Failure Mechanisms Demanding for New Test Methods Ingrid De Wolf, imec Presenter Biography: Ingrid De Wolf (IEEE senior member) received the MS degree in Physics and the PhD in Sciences, Physics, both from the “Katholieke Universiteit Leuven”, Belgium. From 1989 on she joined the Reliability group of imec in Belgium. She worked in the field of reliability physics of semiconductor devices, with special attention for mechanical stress aspects and failure analysis. From beginning 1999 on, she heads the group REMO, where research is focused on reliability, e-test and modelling of 3D technology, BEOL, MEMS, and packaging, including ‘chip-package interaction’. She authored or co-authored in these fields several book chapters and more than 320 publications. She is part time professor at the Metals and Applied Materials engineering department of the KU Leuven. ESD / Latch-up / EOS Support Through Foundry Business in HV Technologies Wolfgang Reinprecht, Austria Microsystems Presenter Biography: Wolfgang Reinprecht is Principal Engineer ESD/EOS at amsAG and responsible for development of ESD protection circuits, libraries and rules in 0.35 and 0.18 µm HV technologies. He supports design engineers to ensure ESD, over voltage and Latch-up robust products. He finished his education in communication engineering and electronics in 1985 in Graz. From 1986 to 1996 he joined AMS as Design & Layout engineer and was responsible for analogue IP block development. 1997 he founded Mikro-Elektronik Design Service GmbH and led the development of IP-blocks, libraries, ESD protections and check tools for various technologies. In 2006 he joined the ESD/ EMC group at amsAG (austriamicrosystems). Since 2010 he is participating in standardization meetings and working groups related to ESD, EOS and Latch-up topics. 5
Invited Talk 3 Invited Talk 4 Abstract: To have the chance to get the “big picture” I want to talk about three important topics: OEM requirements, boardnet and impact to semiconductor. In the first step I want to give an understanding what motivation OEMs have to do a permanent change of their requirements. This will include (beside increase of functionality) the change within existing functions and topologies. Permanent reduction of powerlosses, less weight and less size are three of the side effects. The boardnet as connection between all electrical components has an important role. Any change has impact to the body control module (BCM) and the semiconductors as well. Relay replacement and new voltage domains within the vehicle are examples for this. From semiconductor point of view the main challenges are high currents and transient voltages. Additional miniaturization leads to high power densities and improved diagnosis capability. Additionally reliability has to increase. Abstract: This presentation is focused on ESD challenges for the Fully Depleted SOI (FDSOI) Ultra Thin Body and Box (UTBB) advanced CMOS technology nodes. After an introduction on the FDSOI technology provided by ST, the ESD protection strategy particularities in this technology will be discussed. Principally, performance of elementary devices will be discussed for the hybrid bulk solution. Afterward, the ESD strategy robustness will be elaborated. Change of Electrical Requirements in Automotive Application Andreas Kucher, Infineon Technologies Presenter Biography: Andreas Kucher finished his master study in Telematics at Graz University of Technology in 1997. During his more than 15 years of experience in R&D and Marketing Andreas has worked as an analogue designer, project manager, concept and application engineer. Currently his position is Technical Lead for body applications in automotive. He is Principal at Infineon Technologies. Outside Infineon he likes to ride motorcycles and play hockey. ESD Challenges for FDSOI UTBB Advanced CMOS Technologies Philippe Galy, STMicrolectronics Presenter Biography: Philippe Galy is Senior Expert in micro & nano-electronics at STMicrolectronics R&D, Crolles France since 2005. He proposed a full CDM protection strategy validated by silicon proof. Moreover, its main R&D topics are on SCR, T2, BIMOS transistor, Beta-structure and other innovative devices. Moreover, he proposes several new ESD compact devices with associated trigger circuits for ESD network. He leads several groups in IP infrastructure team for R&D focused from transistor level to the SOC level for robust IP integration. He is serving in the TPC or as a reviewer for many symposia and for TED/SSE. Prior to that, he was a professor at an engineer school for 10 years. He has authored or co-authored several publications, books and patents. He holds a Ph.D. and H.D.R. (academic research supervisor). Monday Evening Talk GRENOBLICIMES Photography book by DiVertiCimes On the borders of Chartreuse, Vercors and Belledonne, the city of Grenoble stretches out over several valleys, surrounded by mountains. When leaving the city to climb the mountains above, one is immediately moved by the contrast between the urban areas and the wild spaces, between the city’s architecture and nature’s generosity. On some winter days, unique local weather conditions cause a vast sea of clouds to form over the metropolis and to shroud the foothills, filling every crack, every gap. Above the sea, the sun asserts itself, revealing a separate world of rare beauty – bathing the emerging mountain tops, the pastures and the villages in its light. This book is an account of the passage to this other world, so close to Grenoble. More than an illustrated report, the DiVertiCimes collective offers a contemplative and artistic approach. They play with light, wait for the ideal weather conditions and create original compositions to present the mountains, as well as the city seen from the mountains, in a new way. This book is meant to prolong this adventure and to share these unique moments with all those who are in love with Grenoble and its surroundings, forever or for a day. Contrary to the solitary approach of most photographers, that of DiVertiCimes is a collective one: six mountaineering photographers or photographing mountaineers who take much pleasure in spending time together, in watching the flight of a butterfly, in feeling a gentle wind, in sharing a good saucisson and some red wine. Six photographers deeply moved by the passing of time and saddened by each minute of lost light. Six photographers who are very playful sometimes, when they position a figure on a mountain top for instance or use umbrellas, as shepherds once did. When back down in the valley, the adventure goes on. The photographs belong to the group and not to the individual any more – as part of some kind of spiritual phalanstery.
Seminars Seminar Chair: Markus Mergens, QPX The six seminars this year address important topics for the changing industry with respect to ESD protection design. The focus on the first seminar day is on system-level ESD, automotive EMC/ESD as well as a comprehensive study on EOS customer returns. The second day of seminars concentrates on GaN ESD concepts including LEDs, the newly proposed ESDA/JEDEC CDM standard, and an overview on the ESD offering from TowerJazz. Seminar 1 System Level On-Chip ESD Protection Vladislav Vashchenko, Maxim Integrated Products Abstract: A significant paradigm shift in systems and analog IC design has been initiated by the new market demands over the last decade. Integration of emerging technologies, increase in data rate, rapid evolution of the portable and mobile devices, lower power consumption and operating voltages, dramatic increase of electronic content in automotive products with 0ppm failure rate target and substantial progress in medical applications have created the demand for on-chip protection against system level ESD and surge stresses. This has impacted ESD specification for analog ICs, has changed understanding of the system standards and test methodologies, that now applied to the component level, as well as has initiated an intensive R&D for a broad range of aspects from new high current capable ESD on-chip devices up to advanced Si TVS components with extremely low parasitic capacitance and precise waveforms. Thus, a new on-chip system level protection ESD design culture has emerged and is evolving further. It involves not only a physical design of the high current capable on-chip devices, but requires to take into account both high voltage and transient Latch-up phenomena, board and system blocks design with off-chip components as well as understanding of the correlation factors for the devices, pulse types and test setups. This trend is ramping up toward creation of a new system-IC co-design approach. The seminar brings a structural physical understanding of the major aspects involved in the modern system level on-chip ESD design. The presentation is organized in five sections that combine (i) introductory material for major principles and methodologies of the system level ESD design, (ii) quintessence of ESD and surge test standards and methods both for on-chip and board level with TVS protection; (iii) describes the essentials of the device and clamp level solutions for the on-chip system level ESD protection, further extended toward (iv) the remaining aspects of the IC design, Latch-up and transient-induced Latch-up and finally concluded by (v) outlining the chip-system co-design approach. Presenter Biography: Dr. Vladislav Vashchenko is Director of ESD group at Maxim Integrated over the last 3 years. His group is responsible for major ESD development aspects across the entire $2.5B revenue enterprise. During previous decade he was leading the ESD group at National Semiconductor Corp. Until year 2000 he was with reliability department of SRI “Pulsar”. He received MS, Engineer-Physicist and “Ph.D. in Physics of Semiconductors” from Moscow Institute of Physics and Technology (1990) followed by “Doctor of Science in Microelectronics” degree (1997). He is author of 147 U.S. patents and over 100 papers in the field, co-author of books “Physical Limitation of Semiconductor Devices” (2008), “ESD Design for Analog Circuits” (2010, www.analogesd.com) and “System Level On-Chip ESD Protection” (in production). Seminar 2 EMC/ESD Design and Characterization for Automotive Applications Patrice Besse, Freescale Semiconductor Abstract: In embedded systems, ESD is considered as an electromagnetic disturbance and it is part of a global electromagnetic compatibility (EMC) specification. EMC tests are mainly performed in powered mode and functional performance of the system is evaluated during and after the stress. In this case, different levels of functionality are required including operating modes, levels of stress and functions. Integration of system functions into IC has brought ESD / EMC system level requirements to the IC level, including functionality performances. Global pins of ICs, directly tied to connectors, are particularly exposed during system level stress. This seminar will discuss the common and specific ESD/EMC system requirements we need to take into account at the IC level. During this seminar, debug and characterization methods to evaluate functional performances of ICs during ESD/EMC system level stress will be detailed. Presenter Biography: Dr Patrice Besse received the Master in electronics in 1999 and then he completed his post master of Electromagnetic Compatibility at Blaise Pascal University, France in 2000. In January 2004, he received the Ph.D. degree in Electronics at the University of Paul Sabatier, Toulouse, France. In 2004, he joined the Analog and Sensor design division of Freescale where he is in charge of ESD/EMI protection strategy for Automotive and industrial applications. Patrice focuses on ESD protection and design optimization to pass ESD/EMC automotive standards at both IC and system level. He is author or co-author of 22 patents and 25 papers in the field of ESD, EMC and reliability. He received the best paper award at EMC compo 2011. 7
Seminar 3 EOS - A Big Challenge in Today‘s Handling of Customer Rejects Gerold Schrittesser, Infineon Technologies Abstract: Handling of customer rejects has become more and more challenging over the years in view of EOS. Unlike ten years ago today most customers are asking for an EOS statement containing a conclusive and comprehensive explanation of the failure scenario that has finally resulted in an “EOS-like” damage and this EOS statement has to be discussed on much higher technical level. On the other hand still today there is not much awareness on the customer side that most “EOS-like” failure signatures do not allow a comprehensive conclusion to the origin of EOS and so the final root cause cannot be evaluated without customer’s support. But in order to be prepared to conduct a successful root cause analysis together with customer the supplier is committed to build up an EOS knowledge base for both internal and external needs. The seminar should deliver insight in today‘s handling of customer rejects in terms of EOS and all the background that is necessary to be successful in that important topic – complemented with a few demonstrative examples. Presenter Biography: In March 1985, Gerold Schrittesser received the masters degree in electrical engineering (with the minor in electro-biomedical engineering and electronics) from the technical university in Graz, Austria. From 1985 to 1995 he was with Siemens AG in Villach, Austria and worked on analog circuit development with focus on ADC converter. In 1996 he joined the automotive power design group as a design engineer and project manager for automotive power ICs. In 1999 he changed to Infineon for another 2 years of circuit design and project management. In 2001 he took over the responsibility for EOS knowledge platform in the automotive quality department with the key aspects EOS knowledge base buildup, customer support and internal coordination in view of EOS topics. Seminar 4 GaN Electronics and Optoelectronics from ESD Perspective Dionyz Pogany, Vienna University of Technology Abstract: Due to wide energy band gap, heterostructure tunability and excellent transport properties, III-nitride semiconductors are promising for opto-electronic, RF, power switching and digital applications. The seminar will start with reviewing the material aspects of III-nitrides and basic designs of heterostructure field effect transistors (HFETs) emphasizing the role of polarization-induced charges and surfaces in channel doping. Potential ESD issues will be linked with the reliability and breakdown behavior. Different parasitic effects like dynamic onresistance, reliability issues like reverse-bias degradation and breakdown mechanisms will be reviewed. For reducing the gate leakage current and achieving normally-off operation of power GaN HFETs, complex gate stacks including oxide insulators are introduced. Thus, gate oxide reliability and threshold voltage instabilities will be discussed. Finally, ESD issues in GaN LEDs and some on-chip protection concepts in GaN-technologies will be reviewed. Presenter Biography: Dionyz Pogany received his “Diploma Engineer” degree in Solid State Engineering from Slovak Technical University in Bratislava, Slovakia in 1987 and PhD degree in microelectronics from INSA de Lyon, France in 1994. Since 1995 he has been with the Institute for Solid State Electronics in Vienna University of Technology where he leads a research team and has been an Associate Professor since 2003. He has been working on Si and III-V device reliability physics, fluctuation phenomena in devices and nanostructures, defect and interface state characterization, GaN HFET electronics and technology, ESD phenomena, self-heating effects, breakdown mechanisms and non-linear transport in ESD protection and Si and GaN power devices, thermal analysis and development of optical methods for device and failure analysis. He published over 100 journal papers and numerous papers on conferences. 8 Seminar 5 The Proposed New ESDA/JEDEC Joint CDM Standard: Considerations, Investigations and Improvements Alan Righter, Analog Devices Abstract: A draft of the new ESDA/JEDEC Joint CDM Standard (JS-002) has been completed and is in review by the standards bodies. This seminar describes the current field-induced CDM testing measurement practice in the industry, differences in the ESDA and JEDEC methods, and describes the issues and improvements from operational, theoretical, measurement, and instrumentation work which have spurred the development of a single CDM test platform for the new standard. Future investigations will also be described. Presenter Biography: Alan Righter is the ESDA Co-chair (along with JEDEC Co-chair Terry Welsher) of the ESDA/JEDEC Standard Joint Working Group (JWG), responsible for development of the new Joint CDM standard. He has worked at Analog Devices, Wilmington, MA since 1997 and currently is a Senior Staff ESD Engineer responsible for ESD robustness of foundry manufactured products and active in customer ESD support. Alan earned a PhD from the University of New Mexico in 1996 and previously worked at Sandia National Laboratories in Albuquerque, NM from 1984-1997. He is currently active on the ESD Association Board of Directors and is also the ESDA Secretary. Seminar 6 Foundry ESD Offering Efraim Aharoni, TowerJazz Abstract: Integrated circuits foundries supply, beyond manufacturing and process technology, also a variety of support items, particularly for the design of ESD protection. This seminar provides a comprehensive overview of the ESD ‘tool-box’ offered by the foundry. It covers a wide spectrum of topics, from the effective ESD team in the organization and ESD/LU-related qualification methodology, to ESD guidelines to designers, required characterization, and verification tools. Special emphasis is put on the Process Design Kit ESD elements like parameterized cells, design rules, models, and protection schemes required for safe design for ESD and short time to market. In addition, the implementation of Programmable Electronic Rule Check (PERC) for ESD is described. The goal of the seminar is to introduce to designers the essential ESD design aids provided by the foundry. Examples are given for miscellaneous technology flavors including Power Management, and different ESD protection concepts based on either snapback devices or RC Rail Clamp. Presenter Biography: Efraim Aharoni received the B.Sc. degree in Physics in 1989 and the Ph.D degree in Physics in 1994 from the Technion, Israel Institute of Technology. His research in the Technion was focused on High Temperature Superconducting devices. In 1993 he joined TowerJazz. Efraim worked in TowerJazz in a variety of fields, in both engineering and management, in development as well as production. Amongst his engineering roles: process, device, yield, director R&D CMOS, and director of reliability. In the past few years, he has led the ESD and Latch-up activities in the company. This involves the development of new ESD devices and protection concepts, creating libraries of ESD devices in PDK, PERC, and customer support. He works closely with the TowerJazz Design Center, device engineers, PDK group, customers, and production lines, in TowerJazz sites worldwide. In addition, he is a member of the Electrical Engineering department in the Kinneret College and lectures on a variety of courses.
Discussion/Special Interest Groups Discussion Group Chairman: Matthew Hogan, Mentor Graphics firstname.lastname@example.org Special Interest Group Chairman: Wolfgang Stadler, Intel Mobile Communications email@example.com The evening discussion groups are an integral part of the workshop, with parallel sessions being offered each evening. Each group has one or more moderators with extensive expertise on the topic, to help guide and inspire the discussion. The success of these sessions depends on your active participation. We encourage you to bring along data, ideas and other items of interest to share. Contacting session moderators with questions, comments or suggestions prior to the event is also encouraged. As the workshop approaches, please check the IEW web site for updates from the group moderators. Interested in forming a new Special Interest Groups (SIGs), focused on one compelling topic of mutual interest? Please contact Wolfgang Stadler, firstname.lastname@example.org for SIG creation details. SIG A.1 DG A.3 The special interest group on ESD technology and EDA parameters addresses the standardization of ESD technology parameter extraction and their representation to facilitate the communication between ESD designers at the product side and technologists especially at foundries. Having a comprehensive and comparable set of ESD parameters in place allows speeding up the design process and ramp-up. This is a win-win for foundries, IP vendors and IC design. A group of ESD specialists from foundry technology and IP / product design have been working on an ESDA White Paper covering this topic which has been published in January 2014. The most relevant aspects of the paper will be presented. Beyond this the idea will be debated whether to proceed with a similar paper describing the standard data useful for interaction between IP vendor and IC design. Latch-up qualification according to JEDEC JESD 78D is mandatory for almost all products. However, today’s complex products often require an enormous effort to set-up a reliable Latch-up stress program, and there is an increasing uncertainty how Latch-up qualification should be conducted today to be compliant to the current standard and in parallel consider the stress limits in the specific application. Only to mention a few, coverage of possible Latch-up sensitive states during the Latch-up stress is under discussion, as well as the practical application of maximum stress voltages (MSV), and current and voltage trigger limits in the test plan. Another question which causes general confusion is how over voltage tolerance should be accounted for in a Latch-up test. And, are the comparably slow Latchup pulses necessarily worst-case Latch-up trigger pulses or do we need faster stress transients, at least for special pins? Come to our Latch-up discussion group, bring your own experiences, problems, and solutions and join our discussion on the most important Latch-up topics! Let the experts of the Latch-up standardization bodies know how future Latch-up standards should be defined to simplify Latchup testing without sacrificing real-world relevance. ESD Technology and EDA Parameters Moderator: Harald Gossner, Intel Mobile Communications email@example.com DG A.2 IEC Standards for EMC Testing Moderator: Agha Jahanzeb, Texas Instruments Inc. firstname.lastname@example.org In addition to the commonly used system level ESD immunity test which is based on the IEC 61000-4-2 specification, there are a number of other IEC 61000-4-x specifications that are also needed as a part of conforming to standard system EMC requirements in many applications and customer needs. These include IEC 61000-4-3, 4-4, 4-5, and 4-6 corresponding respectively to the immunity tests for ‘radiated EM field’, ‘electrical fast transient (EFT)’, ‘surge’, and ‘conducted disturbance from RF’. This discussion group will start by briefly introducing these other system stress tests and draw parallels to the well known ESD test. The audience will be engaged in the discussion by getting their experience and feedback. Finally, we will discuss the degree of relevance to ESD engineers and future involvement. Latch-up Testing Today Moderator: Wolfgang Stadler, Intel Mobile Communications email@example.com DG B.1 Electrical Over Stress at IC and System Levels – which Definition and Events are Related? Moderators: Jean-Luc Lefebvre, Presto Engineering, firstname.lastname@example.org; Christoph Thienel, Bosch, email@example.com; Terry Welsher, Dangelmayer Associates, firstname.lastname@example.org For many years now, industry and standards associations have focused on reducing IC and System degradation due to ESD. Degradation classified as, or due to Electrical Overstress (EOS) represents greater costs at all levels of the industry. This discussion group explores a number of areas. First, how to define EOS? Is it by using its literal meaning? If yes, what does ‘Over’ means? What does Electrical Stress (ES) means? Which type or category of ES event may belong to this EOS definition? What are the root causes of these ES events? If not, what is the best approach of such definition? Failure analysis results? ES events? Root cause events? Are some root cause events already known besides ESD events? Second, how far is the EOS definition at the IC level from the Electro-Magnetic Compatibility (EMC) definition at system level? Does EOS include conductive and field ES and root cause events? Third, how to deal with EOS and EMC events at IC and System levels to reduce failures and degradation? 9
DG B.2 Upcoming ESD Issues Moderator: Charvaka Duvvury, email@example.com Is component level IC protection against ESD becoming a serious challenge due to the seemingly never-ending advances in scaling of silicon technologies? How much is the specific impact from the upcoming technologies such as FinFETs, 3D ICs, and GaN? Further, are the new developments for complex high speed circuits along with the effects from system on chip (SoC) applications making things worse? Add to that, the trend for high pin count IC package development reducing achievable ESD levels as well as making standard test methods more complex. Do they all need an increased attention from the ESD designer? This discussion group will consider the impact of these developments on the “ESD Design Window.” In addition to the necessary component level ESD protection for safe handling at the IC production areas, is the system level ESD protection becoming even more critical because of the high speed demands of USB3 and HDMI interfaces? During the discussion group we will together attempt to bring into focus these technology and performance issues to understand the needed perspective for future research and innovation. The survival of the next generation of electronics industry might very well depend on this proactive attention! DG B.3 Can IP (IO) Validation Guarantee Future IC Products’ ESD Immunity? Moderators: Fabrice Blanc, ARM, firstname.lastname@example.org; Peter de Jong, Synopsys, peter.deJong@synopsys.com How often are you wondering about an IP ESD and Latch-up (LU) immunity for its integration in your products? Or how often have you been doubtful about the pre and post silicon validation of an IP, or unsure about the best practices for your own IP ESD & LU validation? What are the various ESD & LU pre silicon validation methods? • Details required in check reports? • Data to enable the checks by the IP user? What are the various ESD & LU silicon test constraints and requirements? What evidences and assumptions should be detailed in the qualification report? • Based on worst case IP implementation? (Regarding metal stacks, abutments, single/multi-rows,...) • What are pass/fail criteria for sufficient failure detection sensitivity? IC product ESD & LU tests are well covered in test standards but this is not fully applicable or sufficiently detailed for IP level testing. So this is a forum to collect some common practices and requirements and possibly see whether a dedicated standard practice document could help. 10 DG C.1 EOS in Automotive Applications Moderator: Christoph Thienel, Bosch email@example.com In recent years, discussions about Electrical Overstress (EOS) have gained renewed interest. Damage of semiconductors in the automotive industry and in automotive applications is causing a lot of disturbance and pain. Car manufacturers are complaining to suppliers, but the real root causes are out of suppliers´ responsibility in the areas of automotive assembly lines and outside garages. The damage is caused by violation of the semiconductor´s specification. What are the real root causes of EOS? What happened before violation of the specification limit? What are the situations of semiconductor operation if the electronics is destroyed? Which aspects of the whole car are relevant for the damage? Which clusters of root causes do we know? Are there differences between damaging situations in the automotive and consumer industry? If so, what are reasons for it? What is the impact of the applications themselves? Are there damages by applications? What is our imagination and understanding of EOS in general? Is there sufficient experience with EOS in the automotive area? What is the role of ESD? Is ESD also able to damage semiconductors with EOS? Would more ESD protection help against EOS? Let us discuss these topics and spread our questions and experiences amongst each other. DG C.2 The Joint ESDA/JEDEC CDM Standard and Future Roadmap of CDM Moderator: Alan Righter, Analog Devices Alan.Righter@analog.com The in-process joint ESDA/JEDEC CDM Standard (JS-002) is a big step in the harmonization toward a single unified Charged Device Model (CDM) testing standard worldwide. It provides a more accurate and focused description of what is required in field-induced CDM metrology and calibration, as well as its platform hardware limitations. How will the new standard affect your testing of devices, including very small and very large devices? Improvements still need to be made to accurately measure the true CDM waveform at high frequencies. For example, how will improvements such as better hardware implementation of a true 1 ohm discharge resistor, adding cable-based impedance in the discharge path, or improving the field plate dielectric material make a difference in measurements? Also, developments in Contact Charged Device Model (CCDM) and Capacitively Coupled TLP (CC-TLP) point toward more accurate high frequency waveform acquisition. What is their potential to complement or replace more widespread field based CDM methods? Other standards bodies; the Automotive Electronics Council (AEC), Japan Electronics and Information Technology Industries Association (JEITA), and International Electrotechnical Commission (IEC) have their own CDM standards or standard proposals. What are the outstanding roadblocks to unification? Please join us in what promises to be a thought provoking conversation.
Technical Sessions Chairman: Lorenzo Cerati, STMicroelectronics This year’s IEW technical program consists of three sessions, where peer-reviewed poster presentations are discussed together with the authors and interested colleagues. The presentations are all preceded by a set of brief podium “teaser” introduction given by each author in the session. These teasers encourage the workshop participants to visit all posters in the setup area and discuss their ideas and key topics with the authors and each other. A wide variety of ESD subjects will be covered: the first session mainly addresses System-Level ESD issues and characterization techniques; the second session features posters dealing with long-time EOS and system level ESD stresses, and the third session features new trends in ESD testing along with the most advanced technological aspects of ESD protection development. Technical Session A: System-Level ESD A.1 System Efficient ESD Design (SEED) Including 2kΩ/330pF RC Gun Module Jean-Philippe Laine, Patrice Besse, Alain Salles, Freescale Semiconductor SEED methodology implies 100ns TLP information for a safe system level ESD design. Real case with 2k/330pF gun discharge module model show limits of this practice. This paper will present a specific failure mechanism from this gun model and new approach for SEED A.2 Net ESD Characterization by SEED-Style Pin Modeling Benjamin Orr, Pratik Maheshwari, David Pommerenke, Missouri University of Science and Technology; Harald Gossner, Intel Mobile Communications Using SEED-style high voltage SPICE modeling techniques, a MIPI interface consisting of three differential pairs is developed for studies in ESD injection. By modeling both the driver and receivers of each end of the net, as well as the transmission lines between them, predictions can be made about the direction of injected ESD currents. A.3 Transient System-Level ESD Modeling of an Automotive Voltage Regulator Rémi Bèges, Fabrice Caignet, Nicolas Nolhier, LAAS CNRS A voltage regulator model for transient system level ESD simulation, including core description, has been developed with the aim to reproduce the electrical behavior and RESET function during an ESD. Main trends in soft-failure robustness are predictable. This complete model of the component is described and validated by injecting various ESD stresses. A.4 Rationalization of ESD System-Level Stress Characterization of Integrated Circuits A. Salles, P. Besse, J-P. Laine, O. De Barros, J-L Charlet, Freescale Semiconductor In this paper, we intend to share our experience on ESD Gun testing using various setups. Based on tests results, we will propose time saving solutions to identify weaknesses against the whole ESD system level setup that can be required for an Analog IC. A.5 The ‘Other’ IEC Immunity Tests and a Methodology to Model and Improve System Performance Agha Jahanzeb, Rajen Murugan, Jie Chen, Bart Basile, Chris Barr, Mekre Mesganaw, Neil Zhang, Texas Instruments In addition to the commonly used system level ESD immunity test which is based upon the IEC 61000-4-2 specification, there are a number of other IEC 61000-4-x specifications that are also needed as a part of conforming to standard electromagnetic compatibility or EMC requirements. It is the objective of this communication to provide an overview of these ‘other’ IEC tests and discuss techniques of improving the system performance. These methods of protection from these other transient system-level stresses may be similar or different to what are used for the system-level ESD. A.6 Introduction to Fast Transient Characterization Dietmar Walther, Hans-Juergen Rothermel, Torsten Brandes, Texas Instruments Deutschland GmbH; Michael Zwerg, Texas Instruments An introduction to fast transient characterization (FTC) is provided. The FTC is based on equipment from Langer EMV and allows powered-up analysis of a device during direct stressing of pins using fast transient pulses. Good correlation has been found between the FTC method and the system level ESD/EFT performance of a device. A.7 Novel 3D Back-to-Back Diodes ESD Protection B.Courivaud, IPDIA, CNRS-LAAS, Université de Toulouse; N.Nolhier, M.Bafleur, F.Caignet, CNRS-LAAS, Université de Toulouse; G.Ferru, IPDIA A 3D technology is used to design ESD protection devices. Based on back-to-back diodes, these devices are dedicated to first stage, external ESD protection. These devices should be more than robust as existing two dimensional structures regarding ESD stress for a significant area reduction. The specific trench configuration should improve cumulative ESD stress robustness. A.8 Failure Analysis Challenges for 3D Stacked ICs Ingrid De Wolf, imec, KU Leuven; Alain Phommahaxay, Wang Teng, Dimitri Linten, imec; Stefano Guerrieri, Micron Technology This paper discusses some common and new techniques that offer very promising applications for failure analysis (FA) of 3D stacked ICs. Applications include but are not limited to: the location of opens and shorts, barrier breakdown and void detection in TSVs, and failure analysis of a Kelvin structure. 11
Technical Session B: EOS & Characterization B.1 Non-EOS Root Causes of EOS Damage Alan Righter, Ed Wolfe, Jean-Jacques Hajjar, Analog Devices Failure signatures resembling damage from direct electrical overstress (EOS) events may not always have their root cause from an EOS transient. The authors describe examples from packaging and test escapes where the failures had a root cause from another source. Containment or root cause resolution in each case is described. B.2 Transient Latch-up (TLU) Investigations on 12V-Supplied Microcontroller in 0.45μm Technology Andy Noiret, Alexander Schaab, Daniel Jäcksch, Micronas During the qualification of an automotive MCU in 0.45μm technology, several cases of EOS have been found. The strong correlation between the hot switching of an uncharged capacitor on one internally regulated 5V-supply pin and the silicon damages observed indicates a TLU mechanism. This was confirmed with TLP pulses on powered ICs. B.3 Characterization Methodology to Evaluate ESD Clamp Robustness Against EOS Jorge Loayza STMicroelectronics, Ampère; Nicolas Guitard, Blaise Jacquier, Alexandre Dray, Philippe Galy, STMicroelectronics; Bruno Allard, Luong Viêt Phung, Ampère Pre-defined EOS representative waveforms are selected. A methodology is then proposed for characterizing the behavior of protection clamps in these conditions. The objective is to characterize safe-operating area with respect to EOS conditions. Failures of clamps are crucial information for design improvements under targeted EOS specifications. B.4 Wunsch-Bell Based Area Estimation Beyond ESD Stress Michael Mayerhofer, Filippo Magrini, Yiqun Cao Infineon Technologies ESD as a pulsed stress condition is just one of a manifold number of pulses in the automotive industry which can harm integrated circuit products. We demonstrate here a methodology where we use standard 100 ns TLP measurements for ESD estimation combined with Wunsch-bell know how to estimate the minimum area for a dedicated pulsed stress, typically longer than in the ESD case. We demonstrate an ISO7637-2 pulse stress and the application of this advanced method. B.5 100ns-10ms TLP for Investigation of EOS Issues Shuang Zhao, Theo Smedes, NXP Semiconductors As part of the investigation of EOS issues from customer returns, TLP measurements with several pulse widths, from 100ns to 1500ns, have been carried out, and comparable failure signatures have been created that were comparable to those of the customer returned samples. Qualitative correlation can be seen between ESD/EOS failure and the pulse width of TLP measurements. In addition TLP-like measurements with millisecond current pulse have been done. Power-to-Failure vs. Time-to-Failure relation is plotted for both submicron and millisecond TLP results, and fitted by power law respectively for the two different time frames. Good agreement with the Dwyer model has been obtained. 12 B.6 Thin Metal Interconnections Maximum Current Density Definition for ESD Events Leonardo Di Biccari, Fiorella Pozzobon, Giansalvo Pizzo, Andrea Boroni, Lorenzo Cerati, Antonio Andreini, STMicroelectronics The technological scaling is posing more and more stringent constraints on metal interconnection design, especially for advanced smart power technologies, due to the very limited number of available metal levels combined to severe electromigration and System-level ESD requirements. A novel methodology to correctly define and validate the maximum current density for metal interconnections is presented. B.7 Over Voltage Stress (OVS) Test Method Applied on an IC Alain Kamdem, Jean-Luc Lefebvre, Presto Engineering; Fanny Berthet, Patrick Martin, Normandie Universite The electronic industry effort to reduce ESD failure rates has let rise another type of EOS failure, different from ESD, named OVS. Based on that, Presto Engineering starts a consortium called SESAMES with the aim of deepening the understanding of failure mechanisms, ageing and components physical limits caused by OVS. B.8 Test of Zener Diode Under Bi-Exponential Pulsed EOS Feiyi Zhu, François Fouquet, Blaise Ravelo, Moncef Kadi IRSEEM This paper is devoted to the characterization of Zener diode under pulsed bi-exponential electrical overstress (EOS). Experimental tests were conducted for analyzing the diode behavior and the corresponding electrical degradation. Observation on experimental results illustrate the I(V) characteristic modification during the transient EOS time.
Technical Session C: ESD Testing & ESD Protection Development C.1 Low-Cost Unselected Pin Capacitance Suppression for Matrix-Type HBM Testers Sander Sluiter, Theo Smedes, NXP Semiconductors A low-parasitic option for “matrix” type HBM testers has been designed and verified. The results are very promising. However, there are also some concerns. These need to be verified in a follow-up project. C.6 Stacked Power Clamp Design Challenges Alain Loiseau, Robert Gauthier, Ephrem Gebreselasie, Lin Lin, Andreas D. Stricker, IBM When a power supply voltage exceeds the voltage rating of the available power clamps, a common approach is to stack multiple devices. This paper reviews some common problems that can lead to degraded reliability with stacked ESD devices. C.2 Proposal for Statistical Approach to CDM Testing for High Pin-Count Devices Agha Jahanzeb, Texas Instruments; Charvaka Duvvury CDM stress time of high pin-count devices can be excessively long - about an hour and a half for a 1000-pin device at a single voltage. This time quickly adds up to several hours for a few voltage levels with multiple samples required at each level. This stress time can be shortened without sacrificing the quality of test by using a statistical method of sampling. C.7 Unusual Latch-up Phenomenon and a Novel Solution Without an Additional Cost Teruo Suzuki, Fujitsu Semiconductor; Mitsuhiro Tomita, Hiroshi Ikeda, Akiruno Technology Center Unusual Latch-up phenomenon in the microcomputer with a built-in flash memory was found. The root cause was found with TCAD simulation and the Latch-up mechanism was explained. A novel solution without an additional cost was offered. After applying the solution, the Latch-up immunity was improved dramatically. C.3 Comparison Analysis for ESD Failure Between Glass Cleaning Process and Component-Level CDM Test for CMOS Image Sensor Product Han-Gu Kim, Chang-Su Kim, Kyoung-Sik Lim, Geon-Sik Cho, Samsung Electronics Comparison analysis for Electrostatic Discharge (ESD) failure between glass cleaning process and component-level Charged Device Model (CDM) test for CMOS image sensor product is presented in this paper. The ESD failure mechanism for glass cleaning process after assembly is analyzed and the failure location is found by SEM analysis. It is confirmed that the failure points by ESD failure samples both glass cleaning process and CDM test are the same. C.4 Preliminary 3D TCAD Results on Ultra-Compact BIMOS Merged SCR with Current Injector for ESD Protection in Bulk and FDSOI Advanced CMOS Technology Philippe Galy, Johan Bourgeat, STMicroelectronics BIMOS transistor is widely used as dynamic and static ESD protection for advanced CMOS technology. Today, it appears there is a drastic reduction of the Vt1 load for new technology node. To address this new challenge a novel BIMOS merged SCR with PNP current injector is introduced to reduce the triggering voltage of the protection and also to reduce the Vhold. Moreover, to avoid the LU constraint it is possible to adjust Vhold by topology parameter. C.5 Overview of Point to Point ESD Protection Application in CMOS 28nm bulk/FDSOI Technology Johan Bourgeat, Nicolas Guitard, Jean Jimenez, Boris Heitz, Philippe Galy, STMicroelectronics Point to Point ESD protection has already been presented as a good and very efficient solution in self-protected IO in 1.8V This paper presents an extended application of this protection applied to specific IO or IO configuration. The power device, in bulk/hybrid area, is the same and simply the Bimos trigger circuit is adjusted to reach specific needs in deep CMOS technology. 3D TCAD simulations have been realized but only measurements are presented. C.8 ESD Protection of 700V NLDMOS in a 0.35μm Bulk CMOS Process Lutz Steinbeck, X-FAB Dresden GmbH & Co. KG; Angela Konrad, Lars Bergmann, X-FAB Semiconductor Foundries The ESD properties of 700V NLDMOS in a 0.35μm bulk CMOS process were investigated by means of TLP measurements. Options for improving ESD self-protection level and protectability by a parallel clamp and potential ESD protection devices are discussed. Call for Open Posters In parallel to our reviewed poster sessions, all workshop participants are allowed to present open posters to discuss the latest developments in their work. Use this opportunity to discuss new results with your peers before they are in publishable form. Note that the open posters will not be published by the IEW organization in any form. Therefore, discussing your open poster does not impact later publication in any way. Please indicate on the registration form your intention to bring a poster and send your draft by April 30, 2014, to the TPC Chair Lorenzo CERATI at firstname.lastname@example.org. Updates and late submissions are possible until the start of the workshop. For more details on posters at the IEW, see the open-posters section of the IEW website: http:// www.esda.org/IEW.htm. 13
Monday, May 19, 2014 REGISTRATION AND CHECK-IN 12:00 PM-6:00 PM Registration: Pick up badges and handouts. 12:00 PM-10:00 PM Schedule Hôtel check-in: Get room assignment & room key. Monday, May 19, 2014 1:30 PM-2:50 PM Seminar 1 System Level On-Chip ESD Protection Vladislav Vashchenko, Maxim Integrated Products 2:50 PM-3:05 PM 3:05 PM-4:25 PM 4:25 PM-4:40 PM 4:40 PM-6:00 PM 6:00 PM-7:00 PM 7:00 PM-8:30 PM Break Seminar 2 EMC/ESD Design and Characterization for Automotive Applications Patrice Besse, Freescale Semiconductor Break Seminar 3 EOS-A Big Challenge in Today‘s Handling of Customer Rejects Gerold Schrittesser, Infineon Technologies Dinner Evening Talk: GRENOBLICIMES Tuesday, May 20, 2014 8:00 AM-8:10 AM Welcome - Technical Program Introduction 8:10 AM-9:05 AM Keynote: Compact Muon Solenoid (CMS) 9:05 AM-9:50 AM Invited Talk 1: 3D IC Reliability Challenges: New Failure Mechanisms Demanding 9:50 AM-10:10 AM 10:10 AM-10:55 AM for New Test Methods Ingrid De Wolf, imec Break Technical Session A: A.1 System Efficient ESD Design (SEED) including 2kΩ/330pF RC Gun Module Jean-Philippe Laine, Patrice Besse, Alain Salles, Freescale Semiconductor A.2 Net ESD Characterization by SEED-Style Pin Modeling Benjamin Orr, Pratik Maheshwari, David Pommerenke, Missouri University of Science and Technology; Harald Gossner, Intel Mobile Communications A.3 Transient System-Level ESD Modeling of an Automotive Voltage Regulator Rémi Bèges, Fabrice Caignet, Nicolas Nolhier, LAAS CNRS A.4 Rationalization of ESD System-Level Stress Characterization of Integrated Circuits A. Salles, P. Besse, J-P. Laine, O. De Barros, J-L Charlet, Freescale Semiconductor A.5 The ‘Other’ IEC Immunity Tests and a Methodology to Model and Improve System Performance Agha Jahanzeb, Rajen Murugan, Jie Chen, Bart Basile, Chris Barr, Mekre Mesganaw, Neil Zhang, Texas Instruments A.6 Introduction to Fast Transient Characterization Dietmar Walther, Hans-Juergen Rothermel, Torsten Brandes, Michael Zwerg, Texas Instruments A.7 Novel 3D Back-to-Back Diodes ESD Protection B.Courivaud, IPDIA, CNRS-LAAS, Université de Toulouse; N.Nolhier, M.Bafleur, F.Caignet, CNRS-LAAS, Université de Toulouse; G.Ferru IPDIA A.8 Failure Analysis Challenges for 3D Stacked ICs Ingrid De Wolf, imec, KU Leuven; Alain Phommahaxay, Wang Teng, Dimitri Linten, imec; Stefano Guerrieri, Micron Technology 14
Tuesday, May 20, 2014 - continued 10:55 AM-12:15 PM 12:15 PM-1:20 PM 1:20 PM-1:30 PM 1:30 PM-1:35 PM 1:35 PM-2:20 PM Poster Discussion Session A Lunch Open Time Announcements Invited Talk 2: ESD/Latch-Up/EOS Support Through Foundry Business in HV Technologies Wolfgang Reinprecht, Austria Microsystems 2:20 PM-3:05 PM Invited Talk 3: Change of Electrical Requirements in Automotive Application Andreas Kucher, Infineon Technologies 3:05 PM-3:20 PM 3:20 PM-4:05 PM Break Technical Session B: 4:05 PM-5:25 PM 5:25 PM-6:25 PM 6:25 PM-7:25 PM 7:25 PM-8:25PM B.1 Non-EOS Root Causes of EOS Damage Alan Righter, Ed Wolfe, Jean-Jacques Hajjar, Analog Devices B.2 Transient Latch-up (TLU) Investigations on 12V-Supplied Microcontroller in 0.45μm Technology Andy Noiret, Alexander Schaab, Daniel Jäcksch, Micronas B.3 Characterization Methodology to Evaluate ESD Clamp Robustness Against EOS Jorge Loayza, STMicroelectronics, Ampère; Nicolas Guitard, Blaise Jacquier, Alexandre Dray, Philippe Galy, STMicroelectronics; Bruno Allard, Luong Viêt Phung, Ampère B.4 Wunsch-Bell Based Area Estimation Beyond ESD Stress Michael Mayerhofer, Filippo Magrini, Yiqun Cao, Infineon Technologies B.5 100ns-10ms TLP for Investigation of EOS Issues Shuang Zhao, Theo Smedes, NXP Semiconductors B.6 Thin Metal Interconnections Maximum Current Density Definition for ESD Events Leonardo Di Biccari, Fiorella Pozzobon, Giansalvo Pizzo, Andrea Boroni,Lorenzo Cerati, Antonio Andreini, STMicroelectronics B.7 Over Voltage Stress (OVS) Test Method Applied on an IC Alain Kamdem, Jean-Luc Lefebvre, Presto Engineering; Fanny Berthet, Patrick Martin, Normandie Universite B.8 Test of Zener Diode Under Bi-Exponential Pulsed EOS Feiyi Zhu, François Fouquet, Blaise Ravelo, Moncef Kadi, IRSEEM Poster Discussion Session B Discussion/Special Interest Group Session A: Parallel Groups SIG A.1 - ESD Technology and EDA Parameters DG A.2 - IEC Standards for EMC Testing DG A.3 - Latch-up Testing Today Dinner Discussion/Special Interest Group Session B: Parallel Groups DG B.1 - Electrical Over Stress at IC and System Levels – which Definition and Events are Related? DG B.2 - Upcoming ESD Issues DG B.3 - Can IP (IO) Validation Guarantee Future IC Products’ ESD Immunity? Wednesday, May 21, 2014 8:00 AM-8:05 AM Announcements 8:05 AM-8:20 AM 8:20 AM-8:35 AM Reports on DG/SIG Session A Reports on DG/SIG Session B 8:35 AM-9:55 AM 9:55 AM-10:10 AM 10:10 AM-10:25 AM Seminar 4 GaN Electronics and Optoelectronics from ESD Perspective. Dionyz Pogany, Vienna University of Technology Group Picture Break 15
Wednesday, May 21, 2014 continued 10:25 AM-11:45 AM 11:45 AM-12:45 PM 12:45 PM-5:00 PM 5:00 PM-6:00 PM 6:00 PM-7:00 PM 7:00 PM-8:20 PM Seminar 5 The Proposed New ESDA/JEDEC Joint CDM Standard: Considerations, Investigations and Improvements Alan Righter, Analog Devices Lunch Free Time Discussion/Special Interest Group Session C: Parallel Groups DG C.1 - EOS in Automotive Applications DG C.2 - The Joint ESDA/JEDEC CDM Standard and Future Roadmap of CDM Dinner Seminar 6 Foundry ESD Offering Efraim Aharoni, TowerJazz Thursday, May 22, 2014 8:00 AM-8:05 AM Announcements 8:05 AM-8:20 AM Reports on DG/SIG Sessions C 8:20 AM-8:35 AM Industry Council Report 8:35 AM-9:20 AM Invited Talk 4: ESD Challenges for FDSOI UTBB Advanced CMOS Technologies Philippe Galy, STMicrolectronics 9:20 AM-9:40 AM 9:40 AM-10:25 AM Break Technical Session C: C.1 Low-Cost Unselected Pin Capacitance Suppression for Matrix-Type HBM Testers Sander Sluiter, Theo Smedes, NXP Semiconductors C.2 Proposal for Statistical Approach to CDM Testing for High Pin-Count Devices Agha Jahanzeb, Texas Instruments; Charvaka Duvvury C.3 Comparison Analysis for ESD Failure Between Glass Cleaning Process and Component-Level CDM Test for CMOS Image Sensor Product Han-Gu Kim, Chang-Su Kim, Kyoung-Sik Lim, Geon-Sik Cho, Samsung Electronics C.4 Preliminary 3D TCAD Results on Ultra-Compact BIMOS Merged SCR with Current Injector for ESD Protection in Bulk and FDSOI Advanced CMOS Technology Philippe Galy, Johan Bourgeat, STMicroelectronics C.5 Overview of Point to Point ESD Protection Application in CMOS 28nm Bulk/FDSOI Technology Johan Bourgeat, Nicolas Guitard, Jean Jimenez, Boris Heitz, Philippe Galy, STMicroelectronics C.6 Stacked Power Clamp Design Challenges Alain Loiseau, Robert Gauthier, Ephrem Gebreselasie, Lin Lin, Andreas D. Stricker, IBM C.7 Unusual Latch-up Phenomenon and a Novel Solution Without an Additional Cost Teruo Suzuki, Mitsuhiro Tomita, Hiroshi Ikeda, Akiruno Technology Center C.8 ESD Protection of 700V NLDMOS in a 0.35μm Bulk CMOS Process Lutz Steinbeck, X-FAB Dresden GmbH & Co. KG; Angela Konrad, Lars Bergmann, X-FAB Semiconductor Foundries 10:25 AM-10:35 AM 10:35 AM-11:55 AM Poster Discussion Session C By 11:30 AM 11:55 AM-1:00 PM 16 2015 Announcements and Closing Hôtel Check-Out Lunch
Travel Arrangements & Accommodations IEW ACCOMMODATIONS: The Grand Hôtel de Paris is a legend within the Vercors Natural Park. The hôtel, more than a century old, is the oldest and most impressive in the Vercors. The adventure began in 1894 and 6 generations later, the story continues. The traditional restaurant offers high quality, authentic and generous cuisine; The chef innovates with his vision of traditional French dishes. Located in a three-hectare pr
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