Elegant Solutions

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Information about Elegant Solutions

Published on January 24, 2009

Author: FangXuIEEE

Source: slideshare.net

Description

See how I solved problems. Submit yours to save your money!

Solution example 1 Problem: A given AWG hardware setup has limited bandwidth. Hardware performance: 6nS Rise time and >50nS set to 2% Target performance: 2nS rise time and short setting time Solution: Measure the hardware response and use Maximum Entropy Method to generate predistortion which compensates hardware response. DAC + Amplifier + etc. Pre-distorted waveform Desired output Electronic device distortion One cancel the effect of the other Result: Waveform after Compensation Rise time = 2.5nS Preshoot = 0.65% Overshoot = 0.84% Undershoot = 0.50% Setting time = 6.5nS Waveform before compensation Rise time = 6nS Setting time >50nS Compensation waveform by Dr. Fang Xu Customer want to use that hardware to generate a step signal as much as 3 time faster than what the hardware is capable. RAM G n ’ =  ln G n-1 ’-  H t M ( T -H* G n-1 ’)+ G n-1 ’ Optional weighting Transpose matrix H t Emulated target Desired target Response matrix H Guess of result G n ’ Maximizing entropy - +

Solution example 2 Problem: A device generates a 150MHz 2ns pulse train. Solution: In frequency domain, the spectrum of the pulse train is simply a Dirac comb function in frequency-domain with a period of 1/T multiplied by the spectrum of a single impulse. Result: Missing impulse generates higher noise floor and displaced impulse will generate irregular noise floor. By using the 15MHz bandwidth digitizer to measure noise floor, missing impulse could be detected. by Dr. Fang Xu 2ns 6ns Missing impulse a b How to use a digitizer of 15MHz bandwidth to detect missing impulse or displaced impulse. Higher bandwidth digitizer is not applicable due to its’ under-sampling mode. 2ns 6ns a b f Fourier transform of a single impulse Fourier transformof the pulse train

Solution example 3 Problem: A clock source generate a periodic jitter of 100ps. Solution: In frequency domain, components outside the dc, fundamental or harmonics create timing jitter. A filter remove only these components is needed to remove jitter. So tuned rf stubs on PCB are used for this purpose. In time domain, stubs create reflections which allows successive edges been averaged so that the edge movement could cancel each other Result: A low cost solution effectively removes periodic jitter and result to a patented jitter reduction module. by Dr. Fang Xu A device tolerates only 2ps total jitter. Whet is the simplest solution, which removes jitter but preserves all the level characteristics of original clock signal? Device Jitter Device

Solution example 4 Problem: A dozen ADC’s are digitizing the same signal to increase the effective sampling rate. All existing algorithms try to correct converter gain discrepancy in time domain. Clock phase error are generally corrected by tuning delay elements. But these method can not correct phase and gain variations vs. frequency which result in large spurious components in final spectrum. Solution: A deep mathematical analysis delivered a complete resolution in frequency domain by solving linear equations. Result: Algorithm based on mathematical solution significantly reduces spectrum spurs. by Dr. Fang Xu ADC 7 FFT Fs ADC 6 FFT ADC 5 FFT ADC 4 FFT ADC 3 FFT ADC 2 FFT ADC 1 FFT ADC 0 FFT Input N times MxM linear equations Order of data ADC 7 Fs ADC 6 ADC 5 ADC 4 ADC 3 ADC 2 ADC 1 ADC 0 Input Clock generation Data construction 0 100 200 300 400 500 600 700 -120 -100 -80 -60 -40 -20 0 Frequency (MHz) Non harmonic spur = -25dBc SNR = 20dBc 0 100 200 300 400 500 600 700 -120 -100 -80 -60 -40 -20 0 Frequency (MHz) Non harmonic spur = -78dBc SNR = 54dBc

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