Design of a low power asynchronous SRAM in 45nM CMOS

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Information about Design of a low power asynchronous SRAM in 45nM CMOS
Technology

Published on March 2, 2014

Author: desainirav12

Source: slideshare.net

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Research presentation at the 7th IRAJ International Conference on Computer Science and Mechanical Engineering in Pune in December 2013.

Asynchronous SRAM in 45nM CMOS NCSU Free PDK Paper ID: CSMEPUN-1011-033 International Conference on Computer Science and Mechanical Engineering 10th November 2013, Pune Paper presented by: Nirav Desai, Assistant Professor, Dept. of ECE, ITM Universe Work done as a student at the University of Minnesota, Twin Cities Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

Introduction • 6 Transistor SRAM design presented here. • Mainly used in Level 1 cache memories of microprocessors. • Low power and fast speed of memory access are design parameters. • Self timed design to provide immunity to process variations and adaptability to different clock speeds. Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

SRAM Cell Design Design equations for 6T SRAM: 1. Read Operation Stability 2. Write Operation Stability Figure 1: M1, M3 are inverter pull down transistors. M2 and M4 are inverter pull up transistors. M5 and M6 are NMOS access transistors. BL is bit line and WL is word line. Source: Wikipedia 3. Minimum Cell Area 4. Reverse Short Channel Effect Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 110nM PMOS inverter = 220nM NMOS Access = 90nM • NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess=2.4 • Cbitline = 0.747fF for 512 cell array ( Interconnect Parasitics from ASU PTM Website ) Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • • • • NMOS inverter = 150nM PMOS inverter = 555nM NMOS Access = 180nM NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess = 3 Cbitline = 0.747fF Curve shows SRAM cell is close to write failure. Bitline Precharge to less than 1.1V could be explored to increase SNM. Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

Simulation Setup V(word) V(ic) V(write) V(bit) V(qbar) V(bitbar) V(q) • • • • • M0,M1,M3,M4 form the cross coupled inverter pair M5,M6 are access transistors C1, C2 is the bitline capacitance M7 is the precharge switch for bitline ( bit ) - V3 precharges the bitline to 0.8V V6 precharges bitbar and writes a 0 to the cell Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

Timing Waveforms for Characterization • V(write) precharges Cbit to 0.8V via M7 • V(word) disables access transistors M5 and M6 during precharge . • V(qbar) and V(q) are used to generate the butterfly curves. • V(ic) enables M7 during precharge It could be implemented as NOT(V(word)). • V(bitbar) precharges to 0.8V, shows charge pumping when M7 turns off and follows V(qbar) when wordline is enabled. • V(bit) follows V(q) after word line is enabled. • V(bit) precharged to Vdd by V6 V(write) – Applied to source of M7 (precharge switch) V(word) – Wordline Voltage V(qbar) V(q) V(ic) – Enables the precharge switch M7 V(bitbar) V(bit) Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

PASS TRANSISTOR BASED TREE DESIGN 1:8 Row Decoder Tree a2 a1 8 MSB BUFFERS a2 a2 a0 a1 a2 a2 a2 a2 in a1 a0 a1 a2 Similar Tree Decoder for 16 LSB Bits Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

23 = 8 MSB Bits for Word Line Address from Row Buffers TREE DECODER DESIGN 24 = 16 LSB Bits for Word Line Address from Column Buffers Directions of Increasing bit number From row buffer To Word Line Buffer From column buffer Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

PASS TRANSISTOR BASED TREE DESIGN Delay 170 160 W L 110, 158.9 Delay (psec) 150 880 CK 50 OUT IN 140 CK 130 Identical Sizing for NMOS and PMOS to minimize charge injection effects 220, 118.5 5 120 110 100 • Delay drops by ~40ps/2 for every Doubling of transistor widths • Delay drop saturates around 1760, 84.8 1000nM to 89ps • Used W/L of 880/50 for final tree 6 440, 98.8 90 880, 89.3 80 0 500 1000 1500 2000 Transistor Width (nM) Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

TREE DECODER TIMING DIAGRAMS The following waveforms were applied to the row and column selection inputs of the tree decoder Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

TREE DECODER TIMING DIAGRAMS It takes one cycle for initializing the tree decoder after which we get clean pulses for each row output LSB pulse is wider than MSB pulse in bottom figure to allow the tree to clear present state before next Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

TREE DECODER TIMING DIAGRAMS The top waveforms shows the matrix point output where the row and column select inputs are high The output node discharges when the input goes low Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

SRAM TIMING CIRCUIT 110 220 SAE/Write Enable Timing Sequence: 1. Disconnect Precharge 2. Enable Word Line 3. SAE / Write Enable 4. Wait for read/write in Precharge Wordline Enable 5. Disble SAE/Write Enable 6. Disable Wordline 7. Reconnect Precharge and discharge all word lines Read/Write Input Pulse Precharge Disable Pulse Word Line Enable Pulse Read/Write Output Pulse Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

READ WRITE CIRCUIT ( Design by Bong Jin ) Sense Amplifier Write Driver Precharge Circuit Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

READ WRITE CIRCUIT TEST SETUP Single SRAM Cell for simulations Cbit estimate for 512 rows NMOS Switches to allow read without disabling write circuit Bitline Capacitance estimate from ASU PTM Website Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

READ / WRITE TIMING WAVEFORMS Precharge Pulse ( Active Low ) Data Meant to be written to cell Write Enable Pulse Read Enable Pulse Output of Write Buffer Disable output buffer ( tristate logic ) Bitline Bitline Bar Data Output Data Out Bar Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

SRAM Cell Layout Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

2X2 SRAM Array Layout This unit can be replicated in all directions without any changes. LVS check remaining Array Size = 3.7975umX2.4725um GND B0 B0BAR B1 B1BAR WORD 1 VDD WORD 0 GND Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

Final Waveforms and Decoder Layout Left: Top waveform: Bitline and Bitline Bar waveforms for reading a 1 and Right: Layout of pass Transistor based tree decoder Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

References • Digital Integrated Circuits Jan Rabaey, Anantha Chandrakasan, Borivoje Nikolic ( SRAM Cell Design, Decoders, Read Write Circuits ) • CMOS VLSI Design by Weste and Harris ( Butterfly Curves ) • CMOS Circuit Design, Layout and Simulation Baker, Li, Boyce (Decoder Design) • Course slides of Prof. Kia Bazargan ( Precharge Techniques, Decoders, SRAM Cell Design ) Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Cities

References (Contd.) • • • • • • Design of High Performance Microprocessor Circuits by Anantha Chandrakasan, William Bowhill, Frank Fox A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual-Ground Replica Scheme Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim, University of Minnesota ISSCC 2007 Digital Integrated Circuits by Jan Rabaey Large-Scale SRAM Variability Characterization in 45 nm CMOS Zheng Guo, Student Member, IEEE, Andrew Carlson, Member, IEEE, Liang-Teck Pang, Member, IEEE, Kenneth T. Duong, Tsu-Jae King Liu, Fellow, IEEE, Borivoje Nikolic´, Senior Member, IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 11, NOVEMBER 2009 Dama, J.; Lines, A., "GHz Asynchronous SRAM in 65nm," Asynchronous Circuits and Systems, 2009. ASYNC '09. 15th IEEE Symposium on , vol., no., pp.85,94, 17-20 May 2009 doi: 10.1109/ASYNC.2009.23 Prepared by: Nirav Desai Work done as a student at the University of Minnesota, Twin Citie

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