Computer Organisation Part 4

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Information about Computer Organisation Part 4
Technology

Published on July 29, 2009

Author: kalakar_2k

Source: slideshare.net

Description

Computer Organisation by Mukesh Upadhyay from Lachoo Memorial College Jodhpur

BASIC COMPUTER ORGANISATION God’s Organisation Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

CPU TRIODE I/O MEMORY Buses : A Bus (Address Bus) D Bus (Data Bus) C Bus (control Bus) System Buses (Collection of A,B,C) Note : Primary Memory directly addressable by CPU Secondary Memory not directly addressable by CPU Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Memory RAM ROM IOC I/P 1 V FLAG I N T E R F A C E I/P 2 . . . ALU I/P n GPR ACC O/P 1 O/P 2 . . . PC SP O/P m IR I/O TIMING &CONTROL Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com Bus Convention : A/B Bus C Bus Exchange of Information : Unidirectional Note : I / O Control : South Bridge Memory Control : North Bridge Note : Memory which can be change itself is known as register. Note : Every CPU is microprocessor, But every microprocessor is not CPU

Transformation mechanism that transforms the given input into a desired O/P is typically called a PROCESS Entity that perform these task (transformation) is typically called PROCESSOR The method followed where processor is performing a process is typically called PROCESSING (Process is being processed by processor is PROCESSING) Role of Flags : 2 flags are affected when we go for A – B and they are Z (Zero) and B (Borrow). Z B 0 0 A>B 0 1 A<B 1 0 A=B 1 1 X Z . B + Z . B = S1 Z . B = S2 Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

= x + z y Role of Register : Pentium processor contains only 4 register (Register is nothing but a scratch pad memory) x = y + z According to programming language: MOV R0 , y MOV R1 , z ADD R0 , R1 MOV x , R0 L Value R Value Translated by Compiler This is Parse Tree Or Syntax Tree Note : Accumulator is represented by ( R0 / A ) ( Most General Purpose Register ) Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Role of Special Purpose Register (SPR): Program Counter / Instruction Counter ( It holds address of next instruction to be executed ) 101 100 PC 101 Instruction Register Next Instruction’s address is in PC now, instruction at that address is read out and put it in Instruction Register. (Click any where to move) This all process is maintained by Operating System Stack Pointer ( It can not contain address of any empty location and when it not point to any thing than it contain NULL ) Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Role of Instruction Register (IR): 100 100 . . . 1. Fetching of Instruction 2. Decoding of Instruction ( What to do ? ) 3. Fetching of Data ( if any ) 4. Execution 5 Stores Result Machine Operations Machine Operation (M.O.) + (M.O.) + (M.O.) + (M.O.) + . . . = Macro Operation (Micro Operation) ( 1 Instruction Execution ) Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Instruction and Addressing Mode : ADD A , B Operand Operation Classification Zero Addressing Instruction One Addressing Instruction Two Addressing Instruction Three Addressing Instruction Zero Register Processor (C.P.U) OR Stack Oriented Computer OR Zero Register Organised C.P.U Not a single GPR is available not even ACC Single Register Processor Only one Register ACC General Register Organisation More than one register ( ACC + many other register ) Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Given Equation : X = ( A * B ) + ( C * D ) 3 Address Instruction MUL R1 , A B MUL R2 , C D ADD X , R1 R2 MUL A , B MUL C , D ADD A , C MOV X , A In this case we will loose value of A and C therefore not feasible 2 Address Instruction MOV R1 , A MOV R1 , B MOV R2 , C MOV R2 , D MOV R1 , R2 MOV X , R1 1 Address Instruction LOAD A ( R0 A ) MUL B ( R0 R0 * B ) STORE T1 LOAD C MUL D ADD T1 STORE X Note : Implicit operand is ACC / A / R0 Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

0 Address Instruction PUSH A PUSH D D C A A * B PUSH B MUL B C * D A A * B MUL ADD A * B (A*B) + (C*D) PUSH C STORE X C (A*B) + (C*D) (Calculated) A * B X (in Memory) Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

TYPE OPERATOR DESTINATION / SOURCE 1 SOURCE 2 00 ADD / AND 01 SUB / OR 10 MUL / XOR 11 DIV / NOT Instruction Construction : 0 ADD 1 SUB 00 R0 01 R1 10 R2 11 M OPERATOR DESTINATION / SOURCE 1 SOURCE 2 1 2 2 5 bits 000 R0 001 R1 010 R2 . . . . . . 111 R7 0 ARITHEMATIC 1 LOGICAL Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Register Operand Input Output Operand Memory Operand Addressing Mode : ( How you are getting data ) Instruction Operand OR Operator Direct Indirect Immediate Register-Register Indirect Register-Memory Indirect Memory-Memory Indirect Memory-Register Indirect Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

1. ADD[6] Direct Pointer (The address of operand is available in instruction (ORIGINAL WORKING)) At location 6 (0110) , we are having address 9 (1001) of operand (1001011101). 2. Add 6 Immediate (Data is part of instruction , data is not in any register or memory) Here, data is available is Instruction, 6 (0110) is itself is data IADD[6] Indirect (Pointer) At location 6 (0110) , we are having address 9 (1001), of memory location which is having address of operand (1001011101).It means it is concept of pointer to pointer 0110 1001 1001 1001011101 0110 1001 1001 1100 1100 1001011101 Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Implied Mode : ( operand is at CPU’s register ) CMA Compliment ACC. STC Set Carry Immediate Mode : ( data is part of Instruction ) ADD 6 Add 6 to Accumulator Register Mode : ( Operand is available in GPR ) ADD B A  A + B ADD A , B A  A + B ADD R1 R0  R0 + R1 Register Indirect Mode : IADD B A  A + [M]B the content of Memory M whose address is given by register B must be Added to A Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Memory 4096 X 16 PC ( Program Counter ) 1 2 3 . . . . . .16 MAR 1 2 3 . . . 12 1 2 3 1 I OPR MBR 1 1 2 3 . . . . . .16 E AC 1 2 3 . . . . . .16 Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

ADIC BUS CPU CPU VIDEO BUS FSB DVD HOST PORT MAIN MEMORY NORTH BRIDGE AGP PORT AGP POINT MONITOR LOCAL VIDEO MEMORY PCI SLOT PCI BUS IDE SOUTH BRIDGE SCSI ETHERNET USB I R C HDD CD ROM INTERRUPT IO APIC ISA BUS SUPER I/O ISA SLOT FDD BIOS KB RPINTER SOUND CHIP MOUSE COM 1 COM 2 BUSES Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

1 I/O PROCESSOR MEMORY CONTROL 2 O/P PRIMITIVE BUS ARCHITECTURE The drawback of this technique is that a double side bus is needed Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

BACKPLANE BUS PROCESSOR I/O I/O I/O MEMORY SHARED BUS ARCHITECTURE Different i/o has different data transmission protocol and also having different speed (mismatch) for that, and this is all burden taken care by one device Shared Bustypically called Backplane Bus Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Processor Memory Bus (PMB) Processor Memory Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus I/O Bus The previously said bus system is also having disadvantage of CPU Overheads, to remove this we have two type of Level Architecture : 1. 2 Leveled Architecture 2. 3 Leveled Architecture 2 Leveled Architecture Note : Conflicts and Mismatch can be taken care by Bus Adaptor now this not burden for CPU Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Processor Memory Bus (PMB) Processor Memory MBA BA Backplane Bus BA 3 Leveled Architecture Note : PMB is not directly connected to I/O, rather connected to MBA Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Transfer Video camera To PC Proprietary and rest all are Free Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

SU DU Valid Data Data Strobe t3 t4 t2 t1 BUS TRANSFER : Strobe Method Handshake Method Strobe Method : (source initiated) Block Diagram Timing Diagram Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

SU DU Valid Data Data Strobe Strobe Method : (destination initiated) Block Diagram Timing Diagram Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

SU DU Data Bus DAV DAC 2. Handshaking Method : ( Source Initiated ) Block Diagram SU DU DAC DAV 0 1 0 1 Data Valid Data Accept Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com Click for Every Action

Place Data on BUS Enable DAV Accept Data Enable DAC Disable DAV Disable DAV Timing Diagram Valid Data Data DAV DAC Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

2. Handshaking Method : ( Destination Initiated ) Block Diagram SU DU Data Bus DAV RFD SU DU DAC DAV 0 0 1 1 Data Valid Data Accept Ready to Accept Data Click for Every Action Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Ready to accept Data Enable DAC Place Data on BUS Enable DAV Accept Data from Enable DAC Disable DAV Timing Diagram Data Valid Data Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Bus Scheduling : Daisy Chaining Polling Independent Daisy Chaining Bus Control Unit (BCU) U1 U2 Un Bus Grant . . . Bus Request Bus Busy BUS Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Case 1: U1 is requesting for BUS Note: (Sequential processing) Therefore Un have lowest priority and U1 have highest priority. If U1 leave then only other gets the chance. (as shown in diagram) Case 2: U2 is requesting for BUS . . . Case 3: Un is requesting for BUS U1 grab the Bus Bus Control Unit (BCU) U1 U2 Un Bus Grant . . . Bus Request Bus Busy BUS Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Polling 111 000 001 . . . U1 U2 Un Bus Control Unit (BCU) Poll count BR BB 8 devices : 3 poll count 16 devices : 4 poll count Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Independent U1 U2 Un Bus Control Unit (BCU) . . . Poll count Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

START A=0, QN-1=0 M=MULTIPLECAND Q=MULTIPLIER COUNT =N =10 =01 Q0QN-1 =11 =00 A=A+M A=A-M Arithmetic Shift Right A Q QN-1 COUNT=N No COUNT =0 ? Yes STOP Booth Algorithm : (Using 2’s compliment) Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Multiplication Algorithm : (Using Signed Magnitude) START Bs MULTIPICAND B MULTIPLIER Q As = Qs + Bs Qs = Qs + Bs A = 0 , E = 0 SC = n - 1 As Qs E A Q QN =1 QN-1=? =0 EA=A+B SHR EA Q SC=SC-1 Not 0 SC=? =1 STOP Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

Division Algorithm : Basic Steps: “A trial division” is made by subtracting the y register from Accumulator after the subtraction one of the following is executed 1. if Result is – ve the divisor will not go so a ZERO is placed in rightmost bit of the B register and Accumulator is restored. The combined B register and Accumulator are shifted Left. 2. if Result of subtraction is + ve or Zero, then the trail division is succeeded. The Accumulator and B register both are shifted left and then 1 is placed in the right most bit of B. Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

CBest of Luck Krishna Kumar Bohra (KKB), MCA LMCST www.selectall.wordpress.com

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