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Published on September 17, 2007

Author: CoolDude26

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CSCE 613: Fundamentals of VLSI Chip Design:  CSCE 613: Fundamentals of VLSI Chip Design Instructor: Jason D. Bakos Topics for this Lecture:  Topics for this Lecture Semiconductor theory in a nutshell MOSFET devices as switches Transistor-level logic Logic gates IC fabrication SCMOS design rules Cell libraries Elements:  Elements Semiconductors:  Semiconductors Silicon is a group IV element (4 valence electrons, shells: 2, 8, 18, …) Forms covalent bonds with four neighbor atoms (3D cubic crystal lattice) Si is a poor conductor, but conduction characteristics may be altered Add impurities/dopants (replaces silicon atom in lattice): Makes a better conductor Group V element (phosphorus/arsenic) =andgt; 5 valence electrons Leaves an electron free =andgt; n-type semiconductor (electrons, negative carriers) Group III element (boron) =andgt; 3 valence electrons Borrows an electron from neighbor =andgt; p-type semiconductor (holes, positive carriers) forward bias reverse bias + + + + + + - - - - - - P-N junction + - - + + + + + + + - - - - - - MOSFETs:  MOSFETs Diodes not very useful for building logic Metal-oxide-semiconductor structures built onto substrate Diffusion: Inject dopants into substrate Oxidation: Form layer of SiO2 (glass) Deposition and etching: Add aluminum/copper wires body/bulk GROUND NMOS/NFET PMOS/PFET channel shorter length, faster transistor (dist. for electrons) body/bulk HIGH positive voltage (Vdd) negative voltage (rel. to body) (GND) (S/D to body is reverse-biased) - - - + + + + + + - - - current current FETs as Switches:  FETs as Switches NFETs and PFETs can act as switches bulk node not shown CMOS logic CMOS: assuming PU and PN network are perfect switches and switch simultanously, no current flow and no power consumption! 'and structure' 'or structure' Logic Gates:  Logic Gates inv NAND2 NAND3 NOR2 CMOS: complimentary in form and function NMOS devices (positive logic) form pull-down network PMOS devices (negative logic) form pull-up network Implication: CMOS transistor-level logic gates implement functions where may the inputs are inverted (inverting gates) Add inverter at inputs/outputs to create non-inverting gate Compound Gates:  Compound Gates Combine parallel and series structures to form compound gates Example: Use DeMorgan’s law to determine complement (pull-down network): Y A A B B C C D D Pass Transistors/Transmission Gates:  Pass Transistors/Transmission Gates NMOS passes strong 0 (pull-down) PMOS passes strong 1 (pull-up) Pass transistor: Transmission gate: Tristates:  Tristates Multiplexer:  Multiplexer Transmission gate multiplexer Inverting multiplexer Multiplexer:  Multiplexer 4-input multiplexer Latches:  Latches Positive level-sensitive latch Latches:  Latches Positive edge-sensitive latch IC Fabrication:  IC Fabrication Inverter cross-section field oxide IC Fabrication:  IC Fabrication Inverter cross-section with well and substrate contacts (ohmic contact) IC Fabrication:  IC Fabrication Chips are fabricated using set of masks Photolithography Inverter uses 6 layers: n-well, poly, n+ diffusion, p+ diffusion, contact, metal Basic steps oxidize apply photoresist remove photoresist with mask HF acid eats oxide but not photoresist pirana acid eats photoresist ion implantation (diffusion, wells) vapor deposition (poly) plasma etching (metal) IC Fabrication:  IC Fabrication Furnace used to oxidize (900-1200 C) Mask exposes photoresist to light, allowing removal HF acid etch piranha acid etch diffusion (gas) or ion implantation (electric field) HF acid etch IC Fabrication:  IC Fabrication Heavy doped poly is grown with gas in furnace (chemical vapor deposition) Masked used to pattern poly Poly is not affected by ion implantation IC Fabrication:  IC Fabrication Metal is sputtered (with vapor) and plasma etched from mask Layout Design Rules:  Layout Design Rules Design rules define ranges for features Examples: min. wire widths to avoid breaks min. spacings to avoid shorts minimum overlaps to ensure complete overlaps Measured in microns Required for resolution/tolerances of masks Fabrication processes defined by minimum channel width Also minimum width of poly traces Defines 'how fast' a fabrication process is Lambda-based (scalable CMOS) design rules define scalable rules based on l (which is half of the minimum channel length) classes of MOSIS SCMOS rules: SUBMICRON, DEEP SUBMICRON Layout Design Rules:  Layout Design Rules Layout Design Rules:  Layout Design Rules Transistor dimensions are in W/L ratio NFETs are usually twice the width PFETs are usually twice the width of NFETs Holes move more slowly than electrons (must be wider to deliver same current) Layout:  Layout 3-input NAND Design Flow:  Design Flow Design flow is a sequence of steps for design and verification In this course: Describe behaviors with VHDL/Verilog code Simulate behavioral designs Synthesize behaviors into cell-level netlists Simulate netlists with cell-delay models Place-and-route netlists into a physical design Simulate netlists with cell-delay models and wire-delay models Need to define a cell library: Function Electrical characteristics of each cell Layout Cell Library (Snap Together):  Cell Library (Snap Together) Layout

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