bump stress

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Information about bump stress

Published on January 9, 2008

Author: Margherita

Source: authorstream.com

Study of bump stresses:  Study of bump stresses The aim of this study is to check the effect of stresses on bumps due to thermal cycles in realistic conditions dictated by the mechanical layout. The procedure We simulate the module mechanical structure (carbon-carbon + module + kapton circuit) and we concentrate on Indium bumps. We are interested in “real life” and “unavoidable” cycles [i.e. -20C, +20C] and we assume fabrication at room temperature and stress when cold. We want to start and “look” at bumps and their deformation, we then choose a glass tile, measurements will be repeated as soon as “dummy” tiles will be available. We want to maximize the bilaminar effects for a given DT, we then choose a very rigid glue (cyanoacrylate) deposited in a very thin layer. C.Gemme, P.Netchaeva, L.Rossi, E.Ruscino, F.Vernocchi Slide2:  Measurement setup (bare module) Tile = 300 mm thick glass with In bumps Chips = bad FE chips with In bumps (550mm thick). Flipping in Genoa. Measurements at -10C, 0C , +20C and +40C, T measured with IR thermometer. Measurements at edge of tile (in last double column). X-distance between measured points = 58.8mm Displacement measured with microscope. A dozen of cycles [-20C, +20C], measured after each cycle in some cases rising to +40C (90% of time at -20C, i.e. under stress). Periodically checked bump adhesion ( = measure bump gap with microscope focus): OK Measurement points x Carbon-carbon Rigid glue = cyanoacrylate Left edge (low side):  Left edge (low side) Measured at -10C, +20C, +40C the red line represents a fixed position on the chip (recognizable pattern). The distance between the metalization on the glass and this line determines CTE Right edge (low side):  Right edge (low side) Measured at 0C, +20C, +40C Analysis of results:  Analysis of results Max displacement measured on one side (for D T = 50C) is ~7.5 mm. CTE can be calculated using any pair of temperature measurements, results are all compatible with D(CTE)=4.8 ± 0.5 10-6 C-1(i.e. glass CTE = 4.0 10-6 C-1, while silicon is 2.5 10-6 C-1; this means that with glass we are exploring an equivalent silicon DT of ~80C (instead of 50C as for glass). Bump connectivity can only be controlled by measuring the bump gap. This is constant after each cycle and equal to 8 ± 1 mm (typically ~30 mm when bump is disconnected). Connectivity to be checked with dummy silicon modules (bump chains) after similar cycles. x1000 Focused on chip substrate Focused on under-bump metal Image focus displaced by ~8 mm. Effect of Kapton circuit (dressed module):  Effect of Kapton circuit (dressed module) After a dozen of cycles of the bare module in about two weeks a kapton circuit has been added. Patterned kapton circuit (50 mm thick, no coverlay) was glued at room temperature with cyanoacrilate. Measured, then cooled to -20C, then measured again Kapton circuit cyanoacrylate Effect of cooling with kapton:  Effect of cooling with kapton Left +25C Right 0C Right +25C Left -10C Bump detach at 1st cycle 50 mm apart 25 mm apart Back to room temperature:  Back to room temperature All edge modules detach at the 1st cycle at -20C. Measuring at room temperature we find chip/substrate distance of 40 mm and 50 mm (left side at -10C, up and down), 40 mm and 25 mm (right side at 0C, up and down). The module at 0C requires ~15g force applied at the edge of the sensor to bend back to its original shape. One good In bump should resist ~0.1g . The module bends back to its original shape when back to room temperature. Left -10C Left 25C Why kapton circuit so nasty?:  Why kapton circuit so nasty? Kapton circuit contracts considerably with a -40C D T, it bends the 300 mm thick glass and applies a shear/peeling force to the bumps. The tabulated CTE is 16.8 10-6 C-1(Cu), 30-80 10-6 C-1(kapton). We can measure the patterned kapton CTE by comparison of thermal expansion between the 300 mm thick glass (CTE=4 10-6 C-1) and the kapton. The kapton is glued to the glass on one (short) side only. The glass is thermally coupled to a sizeable Cu mass to allow the measurement at ~constant temperature. The kapton will be forced to stay in a plane by a 1mm thick glass placed on it (but free to move). Cu thermal mass thermal grease (glass/kapton)glue Close point (a) Far point (b) Kapton contraction:  Kapton contraction Even with small magnification one can see the relative shift of the far point (b). The distance between the far point and the glue joint is ~60 mm +25C 0C Comparison with glass (at point b):  Comparison with glass (at point b) The lines have been drawn along the pixel columns (metalized dots) and compare glass and kapton contraction. The shift is 60±5 mm over ~60 mm (i.e. one part in 103 for 25 degrees change). CTE(patterned kapton) =(44±4) 10-6 C-1 i.e. the patterned kapton CTE is dominated by the kapton itself. b: +25C b: 0C What to do?:  What to do? Stress on bumps should be minimized (long term effects), this can be obtained either by : looser bond between kapton and silicon, or smaller CTE substrate material (upilex?), or stronger FE/sensor bond (e.g. add a glue bond) Bilaminar effect C-C/silicon seems not to be a problem. Monolithic module . . We start investigating how to include a glue bond to strengthen the FE/sensor link in the critical edge region. We need a bond able to stand >100g of force. Trials with glue on glass samples:  Trials with glue on glass samples Dow Corning 734RTV (tens. strength= 16 Kg/cm2, 321% elongation, CTE~300 10-6 C-1, er~2.5, dielectric rigidity~18KV/mm), and Epotek 353ND (flex. strength= 750 Kg/cm2, CTE=56 10-6 C-1, viscosity = 2000 cps) have been used on glass samples bumped on bad electronics, both glues are fluid and “electronics compatible”. A minimal quantity is applied on two edges (parallel to columns), it enters in between chip and glass by capillary effect. Dow Corning enters <0.5mm, Epotek fills almost everything. Dow Epotek Electronic effects (Epotek 353):  Electronic effects (Epotek 353) Small amount of Araldit353 has been put on glass sample and on a single chip with FE_C (GE_C_7). In both cases glue is deposited at the EoC logic edge (the only accessible for the single chip once mounted on board). EoC logic is here Glue enters as expected (~3-4 mm) Easy to see where the glue entered in the single chip assembly: large threshold changes Other electronics effects:  Other electronics effects Raw data Noise Conclusions:  Conclusions Reinforcing glue (if any) should not enter between FE and sensor but be confined to periphery of the last chip (not more than last column). This is possible with UV curing glue NEA 123 (tens. strength =245kg/cm2; CTE~10-4 C-1, 60% elongation before breaking, dielectric rigidity= 980V/25mm, er=4). Three samples have been glued at periphery with NEA 123 tested to measure the detaching force (~1000 g, fatigue test is ongoing). NEA 123 The capillary effect should be taken into account for the module-to-support glue too. Detailed simulation (including bumps) should be done to explain all described phenomena and guide us in glue choices.

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