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Published on February 7, 2008

Author: Prudenza

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APEX Center - Overview:  APEX Center - Overview Like the art of mountaineering, Semiconductor Technology is a very practically oriented science with very high peaks that few can scale Working professionals in industry are at different levels of height in terms of expertise High-end expertise is to be found only in very small pockets within the industry and academia across the globe Due to fast pace of innovation, Industry and Academia need to come closely together for pursuing Applied Research At BITS-RIT APEX Center, we will attempt to bring together top experts from industry and academia to help the working professionals attain global heights in professional excellence Applied research will be a key focus through close collaboration with industry and top academic institutions Birla Institute of Technology & Science Pilani, Rajasthan Goals:  Goals Birla Institute of Technology & Science Pilani, Rajasthan Education Short Courses to meet specific industry needs Structural Master’s degree program Applied Research PhD Program for working professional & full time students Projects sponsored by Indian & US semiconductor Industry Active research collaboration between RIT & BITS faculty Exchange of researchers between RIT & BITS Program for Professional Excellence:  Program for Professional Excellence Birla Institute of Technology & Science Pilani, Rajasthan A world-class education, training, and hands-on program offered in Bangalore To upgrade skills of VLSI professionals and managers to the world-class level Offered by the best faculty members and industry professionals from India and across the world OLAB extension will be set up at the center in Bangalore with state-of-the-art EDA tools Offered to professionals from Center Affiliates companies The program will consist of multiple courses and access to OLAB Each course will be a complete unit in itself with appropriate credits awarded from BITS - Pilani Accumulation of enough credits and completion of a thesis will entitle for a master’s degree from BITS Will be taught by some of the best faculty and Industry professionals from India and abroad BITS-RIT Collaboration:  BITS-RIT Collaboration Birla Institute of Technology & Science Pilani, Rajasthan BITS will take ownership in setting up the center, the labs, the equipment and the management responsibilities for the center. All investments towards this will come from BITS BITS will also drive the Professional Excellence Program with involvement from faculty from RIT as well as from across the world Award of degrees / certificates for Professional Excellence programs will be managed by BITS RIT will play the lead role in Applied Research, particularly in the area of RF, Analog and Mixed Signal Design with involvement from BITS faculty and others in Industry Prof. P. R. Mukund, Director RAMLAB at RIT will be visiting Bangalore often to supervise the research programs. At least one or more research associates from RAMLAB of RIT will be located in Bangalore to carry on with the applied research work. PhD degrees may be awarded by RIT and BITS jointly or separately depending on the nature of association of the lead researchers BITS and RIT will jointly promote the center Course Structure:  Course Structure Birla Institute of Technology & Science Pilani, Rajasthan Each course will normally be about 20-30 people and will have a tuition fee of about INR 10K – 30K per course per student (including access to OLAB as well) These courses will be offered as intensive courses (10 to 30 hours of teaching over a period of one, two or three weeks), or over a semester Corporate Sponsors:  Corporate Sponsors Birla Institute of Technology & Science Pilani, Rajasthan Each interested company will become a Corporate Sponsor for the Center with an annual fee of INR 75K – INR 200K based on their employee strength Corporate Sponsors will also be able to provide input on courses offered and choice of faculty members Corporate Sponsors will ensure that the Center remains world class and dynamic Annual Corporate Sponsorship Fee Employee Strength < 50 : INR 75K Employee Strength 50-100 : INR 125K Employee Strength > 100 : INR 200K Corporate Sponsorship Benefits :  Corporate Sponsorship Benefits Professionals from Sponsor Companies will be given preference in enrollment in these courses Representatives from sponsor Companies will be invited to be a member of the Technical Advisory Board to guide the Center to meet their specific needs and the needs of Indian Semiconductor Industry. Professionals from their companies would be able to enroll for an M. Eng. Degree from BITS and credit these courses towards their degree program. Resources of the center will be extended for research and development including supervision for Ph.D. programs. Corporate Sponsor will be able to directly benefit from this activity. Birla Institute of Technology & Science Pilani, Rajasthan Suggested List of Courses:  Suggested List of Courses Birla Institute of Technology & Science Pilani, Rajasthan Suggested List of Courses …:  Suggested List of Courses … Birla Institute of Technology & Science Pilani, Rajasthan Suggested List of Courses …:  Suggested List of Courses … Birla Institute of Technology & Science Pilani, Rajasthan Other Possible Courses …:  Other Possible Courses … In addition to the courses on VLSI, the scope may be expanded to offer additional practice oriented courses relevant for Industry Few Practitioner’s Courses identified Software Testing Technical Writing Embedded SW development Bio-Technology Birla Institute of Technology & Science Pilani, Rajasthan Value Proposition for Professionals:  Value Proposition for Professionals Never before opportunity to enrich knowledge and expertise where it matters Learn from best in class experts from all over the world, right here Opportunity for people not having a Masters degree to earn one through part-time route Opportunity for pursuing research through PhD enrollments, while working A stronger alternative to distance learning options available from US based universities Birla Institute of Technology & Science Pilani, Rajasthan Value Proposition for Industry:  Value Proposition for Industry Move up the value chain through skills and expertise gained Possible avenue for better employee retention Compelling cost structure to try new ideas Excellent design infrastructure Instant access to university expertise on fundamental knowledge Birla Institute of Technology & Science Pilani, Rajasthan Value Proposition for Faculty:  Value Proposition for Faculty Chance to contribute to India’s success – especially for NRI industry professionals & professors coming from overseas Chance for strategic relationship with Indian University system Joint research programs with BITS and working professionals from industry in India Better understanding of the emerging markets Opportunity for fulfilling the passion for teaching World class remuneration Birla Institute of Technology & Science Pilani, Rajasthan Value Proposition for Academia :  Value Proposition for Academia Through continuous interaction and help from the top experts participating in BITS-RIT APEX programs, academic curriculums at the University will be constantly enhanced to keep pace with the latest Some of the courses offered at BITS-RIT APEX center will be beamed remotely to the university campuses through video conferencing with an option for the students at the campus to enroll against credits. BITS may consider extending such facilities to other interested universities as well at a future date Plan to fund fundamental and applied research at the university with the resources generated at the BITS-RIT APEX center Chance to contribute to growth of India’s semiconductor industry by facilitating high end talent generation and applied research programs Birla Institute of Technology & Science Pilani, Rajasthan BITS - Pilani :  BITS - Pilani OLAB (Oysters Lab) VLSI DESIGN LABORATORY Integrated efforts of BITS, BITS Alumni and Industry Professionals Birla Institute of Technology & Science Pilani, Rajasthan Slide18:  OLAB at BITS, Pilani Slide19:  OLAB - Industry Sponsors Open Silicon CADENCE Mentor Graphics SUN Microsystems WIPRO Slide20:  OLAB FACILITIES Slide21:  A powerful centralized compute server farm for EDA tools in Layer 1 Sun Fire v250, NAS 3300 & SDLT320 Sun Ray software EDA tools & user files Automatic tape back-up Slide22:  Number of powerful SUNSPARC workstations as compute servers in layer 2 : 20 Ultra 2 Enterprise server-class workstations Computing share through Sun Grid Engine 40 SUN THIN Clients as nodes in layer 3. Connected with 1.0 Gbps network connectivity Slide23:  Tool Suite from MAGMA (About 15 sets of licenses of back-end design tools for mixed signal and a complete package for RTL to GDS flow) Tool Suite From CADENCE Foundry access for fabrication of parts FPGA design infrastructure for prototyping Slide24:  OLAB ACTIVITIES Students of M.E. Microelectronics for conducting laboratory sessions Students of First Degree Programme for courses in the area of VLSI Design To Facilitate Research activities To conduct short term courses for Industry Professionals To support entrepreneurs in Technology Development To undertake Industry Sponsored Projects A Sample list Dissertation projects:  A Sample list Dissertation projects Design of CISC Microprocessor ( M68010 compatible) Design of Application Specific Instruction set Processor for text to speech conversion Design of A/D and D/A converters Design of switched capacitor circuits Design of a CAD tool for synthesis of OPAMPs Currently a Project on ZigBee enabled wireless sensor network is taken up with joint efforts of faculty, students and BITS Alumni. :  Currently a Project on ZigBee enabled wireless sensor network is taken up with joint efforts of faculty, students and BITS Alumni. Slide27:  Master/Controller module Sensor/Slave module Processors and wireless transceivers are the same for both the master and slave modules. Sensor/Slave module WIRELESS MESHED SENSOR NETWORK ARCHITECTURE OLAB will support a full chip design capability at BITS through state-of-the-art EDA tools :  OLAB will support a full chip design capability at BITS through state-of-the-art EDA tools RF/Analog/Mixed Signal Lab (RAMLAB) :  RF/Analog/Mixed Signal Lab (RAMLAB) RF/Analog/Mixed signal Laboratory (RAMLAB) Dept. of Electrical Engineering Building 9, 3rd Floor, Room 3271 Rochester Institute of Technology Rochester, NY 14623 RAMLAB - Overview:  RAMLAB - Overview Industry Liaisons RAMLAB specializes in developing cutting edge design solutions for RF, analog and mixed signal circuits People: Research Faculty Graduate Students Distinguished Researcher Equipment: Unix Workstations with Cadence Suite ATE with probe station, spectrum analyzer & Network Analyzer for RF Characterization Technology Used: 0.25 um TSMC CMOS 0.25 um IBM CMOS Ph.D. Students Anand Gopalan Sripriya Bandi Tejasvi Das Sharmila Sridharan Mark Pude Jeff Lillie RAMLAB - Current Projects:  Chip-Package Co-Design Of RF-Mixed signal Microsystems Built in Self Test Strategies for RF/Mixed Signal Systems High-speed circuit design and Characterization Mixed-Signal IC Design beyond 10 GHz RAMLAB - Current Projects Work with Harris Corporation:  Work with Harris Corporation RF Front end circuitry is designed to be either only narrowband or wideband. For military applications wherein frequency hopping is popular for secure communications, the above mentioned circuitry is not suitable. Objective: design tunable RF LNA with very wide frequency range and very fine selectivity Tunable Wideband LNA Design LNA Schematic Simulation results summary Simulation Results Noise Figure v/s frequency Input return loss S11 v/s frequency Collaboration with Harris Corporation LNA was fabricated on a 10mm^2 Chip using IBM’s 0.25um CMOS RF 6-metal layer process Chip-Package Co-Design of RF Microsystems :  Chip-Package Co-Design of RF Microsystems Convert intricate analysis into a set of simple design rules that can be used by the designer Make trade-off analysis simpler Make intricate problems opaque to the designer First Time Right Lower time to market Research Objectives “To analyze different functional blocks in a RF microsystem, in the 2-5GHz range for Chip-Package Co-Design, and develop a software package that performs early analysis of various functional blocks” Accomplishments Circuit Components Designed and Fabricated using IBM’s 0.25um CMOS Low Noise Amplifier Single Balanced Mixer Low Phase Noise VCO Early Design Software Developed for Chip-Package Co-Design – ‘DREAM’ Suited for ‘Early Design’ Applications are diverse including RF, Mixed Signal, Digital and Power Distribution Integrated Passive Design Embedded Inductor on Si Substrates Developed Inductor Library for Embedded Process Development of Design Rules& Methodologies Design constraints of ESD protection circuitry Vertically Integrated Designs Developed G. Nayak, P.R. Mukund, “Chip-Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using embedded passives in a silicon package”, 17th International Conference on VLSI Design and 3rd International Conference on Embedded Systems, Mumbai, India, January 2004 Chip-Package Co-Design DREAM: Digital-RF Early Analysis Methodology:  Inductor Library Design Methodologies Inductor Modeling and Characterization Inductor Libraries for RF Design Vertically Integrated Designs (Si on Si) Passive Characterization Novel Design Techniques DREAM: Digital-RF Early Analysis Methodology Application Specific Reduced Order Modeling Technique:  Application Specific Reduced Order Modeling Technique G. Nayak, C. Washburn, P.R. Mukund, “System in a Package Design of a RF Front End System using Application Specific Reduced Order Models ”,Accepted at the 18th International Conference on VLSI Design and 4th International Conference on Embedded Systems, Calcutta, India, January 2005 S-parameters comparison with and without package parasitics Proposed SiP Design Methodology Equivalent circuit model for ground pin Model Reduction for power pin Model Reduction for signal pin Built-In-Self Test (BiST) for RF systems:  Built-In-Self Test (BiST) for RF systems Motivation – RF Testing Challenges :  Motivation – RF Testing Challenges Slide38:  Current sensor for GHz applications Requirements of a sensor High Bandwidth Low Sensitivity to process variations High Dynamic Range High Sensitivity Stage 1: Sensing Resistor (Rs) + Source Follower Stage 2: Inverting Amplifier Stage 3: Current Amplifying Cell DESIGN FEATURES Sensing Resistor – 7 Ω Feedback structure Reduction in number of Gain Stages Addition of bypass capacitor BiST for LNA, Mixer, VCO:  BiST for LNA, Mixer, VCO Low real estate and power overheads!! Similar techniques can be used to quantify Output Match (S22), Gain (S21), and Linearity (1dB compression) of LNA Entire self-test can be carried out in less than 20μs. 1.9GHz LNA and BIST circuit fabricated in IBM 0.25 micron Self-Calibrating RF circuits:  Self-Calibrating RF circuits Wide tolerance ranges of package parasitics Dependence of E.S.D. protection on environmental conditions Package portability Design time and cost Hence, a circuit topology that dynamically self-corrects its performance in the presence of process faults and package parasitics is desired! Self-Calibration: Methodology:  Self-Calibration: Methodology Self-correction on-the-fly Non-intrusive current sensing Baseband processing Robust -> Two-tonal approach Cuts down design cycle cost and time Low overheads Self-Calibration: Results:  Self-Calibration: Results LSI Logic: High-speed circuit design and Characterization:  LSI Logic: High-speed circuit design and Characterization Collaborative effort with LSI for device characterization in high-speed circuits. Current empirical models require that every device size used in design has to be fabricated and the data curve-fitted. Model scalability with respect to both device size and technology is required. 0.18um, 0.13um, 90nm & 65nm foundry and data access from LSI Kawasaki: Mixed-Signal IC Design beyond 10 GHz:  Kawasaki: Mixed-Signal IC Design beyond 10 GHz 3-year project begins May 2005 Switching noise dependencies on logic activity and packaging High speed clock distribution in a large chip Simultaneous switching outputs and containment strategies Analog and digital isolation in a SoC design Circuit techniques to monitor core noise Slide45:  Birla Institute of Technology & Science Pilani, Rajasthan Thank You

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