BHallTalk110601Rev3

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Published on December 1, 2007

Author: Jacqueline

Source: authorstream.com

Development of a Readout Technique for the High Data Rate BTeV Pixel Detector at Fermilab:  NSS 2001 November 6th, 2001 B.K. Hall, J.A. Appel, G. Cardoso, D.C. Christian, J. Hoff, S.W. Kwan A. Mekkaoui, R. Yarema, S. Zimmermann Fermi National Accelerator Laboratory Batavia, IL 60510 USA bhall@fnal.gov Development of a Readout Technique for the High Data Rate BTeV Pixel Detector at Fermilab Work supported by the U.S. Department of Energy under contract No. DE-AC02-76CH03000. Fermilab Conf-01/335 Slide2:  Introduction Overview of BTeV system and pixel detector. ~22 million pixel channels, 7620 front end readout chips. Design Constraints Mechanical and electrical constraints imposed by the BTeV pixel detector environment. Simulation Studies Understand the bandwidth requirements. Design Solution Provides a total bandwidth of 2 Tbps directly off front end readout chips. Outline Slide3:  ~22 million pixel channels. 30 pixel detector stations. Each pixel station consists of 44 pixel modules. Each pixel module consists of either 4, 5, 6, or 8 FPIX readout chips and silicon sensors. BTeV System Room for cabling outside tracking region and room for electronics crates behind magnet. Slide4:  Anatomy of a Pixel Station Modules are a sandwich of FPIX readout chips, silicon pixel sensors, and high density flex circuit. FPIX core digitizes analog signal from 128x22 pixel sensor into 23 bit core data words. Connectors (not shown) at ends of flex circuit connect to vacuum feedthrough boards. High density flex circuit brings power, control and data signals to/from FPIX chips. Slide5:  High readout efficiency required – Data is used in lowest level BTeV trigger to reconstruct tracks. High radiation environment – Must be rad-hard components. Inaccessible – motivation for designing a reliable/robust readout system. Max flex circuit width – Can’t interfere with adjacent modules. Need to minimize number of data lines. Data is driven 10 meters – limits data readout speed. Readout Design Constraints Slide6:  Simulations 1st step in design process is to understand how much data needs to be moved out of the FPIX core. Average core data rates for worst case module (module closest to beam) based on GEANT simulation data are shown. Slide7:  Readout Design Solution – Key Features All signaling is low voltage differential (LVDS) – Immune to common mode noise, easy to drive 10m, and can be driven and received by today’s FPGAs. Data paths are point to point for reliablity. Data is serialized – Core data word is formatted then serialized to save data lines. Configurable number of serializers – High data rate chips with 6 serializers while lower data rate chips use a few as 1 serializer. Match core bandwidth to total bandwidth of serializers – Core operating frequency depends on configuration. Simple word alignment scheme for receiver. Slide8:  Readout Design Solution – Configurable Number of Serializers Four possible FPIX configurations. 6 serializers allows FPIX to run at its maximum core operating frequency (34.7MHz). Core operating frequency is a division of serializer frequency (138.8Mhz) by the number of bits each serializer serializes. Slide9:  Simulations were run on Verilog model of FPIX core to determine minimum number of serializers while still maintaining high readout efficiency. Verilog Simulations Determine Optimal Configuration Slide10:  How Receiver Determines Word Boundaries Five bit column address two LSBs guaranteed never to be ’00’. Periphery modifies core data word – Adds word mark bit, reorganizes word. Periphery provides sync/status word when core has no data. Unique sequence of 14 bits in sync/status word. Slide11:  Data Latch Clock and Example Waveform Both edges of DLCLK used by receiving FPGA to latch data. Slide12:  Table of Interesting Totals Slide13:  Summary Readout design offers 2 Tbps bandwidth for BTeV pixel detector. Configurable readout bandwidth to optimize data path width. Only one rad-hard component necessary (FPIX itself) – digitizes, serializes, drives 138.8 Mbps 10m. >98% readout efficiency adequate for BTeV trigger system for track reconstruction. Rapid recovery from data transmission errors – simple word alignment technique, no handshaking required. FPIX with this readout design to be submitted by Jan ’02. Thank You!

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