Altera

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Published on November 28, 2007

Author: Barbara

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History of Programmable Logic:  Robert Blake Vice President, Product Planning History of Programmable Logic Altera Founded in 1983:  Altera Founded in 1983 “The probabilities are high that someone will produce an electrically alterable logic array” predicted Bob Hartmann, Paul Newhagen and Michael Magranet in the closing chapters of their 1982 book on the gate array industry They recognized limitations of ASICs and the value of PROGRAMABILITY History of PLDs - 1984:  History of PLDs - 1984 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD History of PLDs: 1985 - 1987:  History of PLDs: 1985 - 1987 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 CMOS PLD $B History of PLDs: 1988:  Simple Control Logic History of PLDs: 1988 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD ALTR IPO TTL LIB EP1200 EPB1400 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B History of PLDs: 1989:  Simple Control Logic History of PLDs: 1989 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 ALTR IPO AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B History of PLDs: 1990-1991:  Complex Logic Simple Control Logic History of PLDs: 1990-1991 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 MAX+PLUS II MAX 7000 ALTR IPO AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B History of PLDs: 1992:  Complex Logic Simple Control Logic History of PLDs: 1992 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 FLEX 8000 ACCESS EDA ALTR IPO MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B History of PLDs: 1993-1994:  Complex Logic System Logic Simple Control Logic History of PLDs: 1993-1994 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 7032V MAX 9000 ALTR IPO FLEX 8000 ACCESS EDA MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B History of PLDs: 1995:  Simple Control Logic SOPC Complex Logic System Logic History of PLDs: 1995 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 7032V MAX 9000 ALTR IPO FLEX 8000 ACCESS EDA MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B FLEX 10K IP Library FLEX 10K World’s-First FPGA with Embedded RAM History of PLDs: 1996-1998:  Complex Logic SOPC System Logic Simple Control Logic History of PLDs: 1996-1998 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 FLEX 10KA FLEX10KE MAX 7000A ALTR IPO MAX+PLUS II MAX 7000 AHDL FLEX 10K IP Library 0.5 1.0 1.5 2.0 2.5 3.0 7032V MAX 9000 FLEX 8000 ACCESS EDA CMOS PLD $B History of PLDs: 1999:  Complex Logic SOPC System Logic Simple Control Logic History of PLDs: 1999 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 FLEX 10K IP Library FLEX 10KA FLEX10KE MAX 7000A APEX ALTR IPO MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 7032V MAX 9000 FLEX 8000 ACCESS EDA CMOS PLD $B History of PLDs: 2000-2001:  Complex Logic SOPC System Logic Simple Control Logic History of PLDs: 2000-2001 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 FLEX 10K IP Library FLEX 10KA FLEX10KE MAX 7000A APEX Mercury ARM Nios ALTR IPO MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 7032V MAX 9000 FLEX 8000 ACCESS EDA CMOS PLD $B History of PLDs: 2002-2003:  Complex Logic SOPC System Logic Simple Control Logic History of PLDs: 2002-2003 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 99 00 01 02 03 83 First PLD TTL LIB EP1200 EPB1400 FLEX 10K IP Library FLEX 10KA FLEX10KE MAX 7000A Stratix Transceivers Cyclone ALTR IPO Mercury ARM Nios MAX+PLUS II MAX 7000 AHDL 0.5 1.0 1.5 2.0 2.5 3.0 CMOS PLD $B 7032V MAX 9000 FLEX 8000 ACCESS EDA APEX PLD Market Growth – 2003-2007:  ~$5 Billion MOS PLD Market in 5 Years PLD Market Growth – 2003-2007 84 85 87 88 93 86 89 90 91 92 94 95 96 97 98 00 02 05 07 83 99 01 03 04 06 7.0 6.0 5.0 4.0 3.0 2.0 1.0 Quadratic Curve Fit Y = 11.3X2-34X-4.39 15 Copyright © 2003 Altera Corporation CMOS PLD $B Highlights:  Highlights Founded in 1983 $711 Million in 2002 Sales 1,958 Employees 14,000+ Worldwide Customers ALTR (Nasdaq) PLD Growth Opportunity:  PLD Growth Opportunity Jordan Plofsky Sr. Vice President Why PLDs Are a Good Business to Be in:  Why PLDs Are a Good Business to Be in Where Semiconductor Technology Will Take Us Development Costs Trends: ASSPs & ASICs Impact of This Trend Learning Curve Drives Moore’s Law:  1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1995 1993 1994 1996 1997 1998 1999 2000 2001 Traditional 68% Slope Post Recessionary Price Strengthening Excess Capacity Price Erosion Trade Agreement Strong Demand Weak Supply Excess Capacity Price Erosion 1 10 100 1,000 10,000 100,000 0.01 0.1 1 10 100 Price per Bit (Millicents) Cumulative Volume (Bit x 1012) Learning Curve Drives Moore’s Law “In the Box” Advances Will Carry Us through 65 Nanometers:  Multiple Resolution Enhancement Techniques Optical Proximity Correction Scattering Bars Attenuated Phase Shift Double-Exposure Dipole Strong Phase Shift Low K Dielectrics “In the Box” Advances Will Carry Us through 65 Nanometers 1 10 100 1,000 10,000 1980 3.0µ 2.0µ 1.0µ .6µ .35µ Silicon Features (µm) 1985 1987 1992 1996 2000 2002 2004 2007 1998 Silicon Feature Size Lithography Wavelength 436nm 365nm 248nm 193nm 157nm Digital ASSP Business Model:  Digital ASSP Business Model R&D Spending $30M R&D as % of Revenue Revenue Market Share Resulting Market Size Development Cost Simulation:  Development Cost Simulation No Special Design Complexity MXS, CAM, PLLs, Exotic I/O Does Not Include Costs for Architecture Planning Methodology DB Management Version Control New Tools Learning Program Management Verification/Integration for Complex IP IP Acquisition Increased Skilled Engineers * Normalized to Approx 8 mm x 8 mm Die Size 60% Routing Utilization, Artisan Library Development Costs per Engineering Man Year (Fully Loaded):  Development Costs per Engineering Man Year (Fully Loaded) 1997 .35µ 2001 .13µ 2002 .13µ 2003 .09µ 2005 .065µ 1999 .18µ 1998 .25µ 2000 .15µ $150K $160K $170K $180K $190K $200K $225K Signal Integrity 3D Extraction Power Drop Labor – Increased Skill Set Compute Power Increased File Size Storage Test Coverage IP Integration/Reuse Rising Cost of Development:  0.35 µ 0.25 µ 0.18 µ 0.15 µ 0.13 µ 0.09 µ Technology 0.35 µ 0.25 µ 0.18 µ 0.15 µ 0.13 µ 0.09 µ Technology RTL Gates Qtr./Person Verification Qtr./Person Synthesis + P&R Qtr./Person Engineering Man Years 30K 36K 50K 75K 110K 150K 15K 18K 25K 38K 55K 75K 125K 300K 500K 750K 1.0M 1.25M 14 30 38 41 46 52 Engineering Costs ($Ms) Masks & Wafers ($) 2 5 6.4 7.3 8.8 10.4 80K 160K 400K 600K 900K 1.3M Rising Cost of Development ASSP Development Cost at 90nm:  ASSP Development Cost at 90nm * FSA, IBS Development Cost Projection What VC’s Are Saying:  What VC’s Are Saying Raza Foundries $50M in Funding Spectacular Team Needs to Generate $500M over 4 Years Tallwood $25M at .13m $40M at .09m Digital ASSP Business Model:  Digital ASSP Business Model R&D Spending $30M R&D as % of Revenue 20% Revenue $150M Digital ASSP Business Model:  R&D Spending $30M R&D as % of Revenue 20% Revenue $150M Market Share 10% Resulting Market Size $1.5B Digital ASSP Business Model Sizing It Up:  Sizing It Up R&D Spending $30M R&D as % of Revenue 20% Revenue $150M Market Share 10% Resulting Market Size $1.5B The Market Must be Really Big -- or You Have to Own It! 90nm, 300mm:  90nm, 300mm Die Size Normalized to 4M Gates, 4 Mbits Memory Costs to Amortize over Unit Volume:  Costs to Amortize over Unit Volume $30M Development Cost – 15% Hurdle, 5 Yr Return, $7500 300mm Wafer Cost 4M Gate, 4Mb Design 5.7mm x 5.7mm Die Slide32:  Communications $30.6B Consumer $24.1B Computer Storage Peripherals $ 92.9B Industrial Automotive Mil/Aero $26B Let’s Look at the Semi Content in End Markets 2003 Projected Total: $173.6 B Source: Gartner, SIA, Semico, IDC, Altera Estimates Slide33:  Memory $37.2B Processors $46.5B Analog Discrete Opto $ 52.2 B Logic $37.7B Semis by Function 2003 Projected Total: $173.6 B Logic Is 21.8% of Total Source: Gartner, SIA, Semico, IDC, Altera Estimates Communications - $30.6 Billion:  Communications - $30.6 Billion Consumer - $24.1 Billion:  Consumer - $24.1 Billion Industrial, Automotive, Military/Aero - $26.1 Billion:  Industrial, Automotive, Military/Aero - $26.1 Billion Computer, Storage, Peripherals $92.9 Billion:  Computer, Storage, Peripherals $92.9 Billion Summary:  Summary Diverging Development Costs & Revenues in Mobile BTS Equipment:  Mobile BTS Diverging Development Costs & Revenues in Mobile BTS Equipment ASIC/ASSP Logic Development Costs Outpace End-Market Growth 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 Normalized Growth Compared Growth Rates 1997 Index = 1.00 Diverging Development Costs & Revenues in Networking:  1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 Development Costs Outpace End-Market Growth ASIC/ASSP Logic Networking Diverging Development Costs & Revenues in Networking 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 Normalized Growth Compared Growth Rates 1997 Index = 1.00 Diverging Development Costs & Revenues in Digital Consumer:  Diverging Development Costs & Revenues in Digital Consumer Next-Generation Digital Consumer ASIC/ASSP Logic 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 Normalized Growth Compared Growth Rates 1997 Index = 1.00 Development Costs Outpace End-Market Growth Diverging Development Costs & Revenues in Industrial:  Diverging Development Costs & Revenues in Industrial 0.00 0.50 1.00 1.50 2.00 2.50 3.00 1997 1998 1999 2000 2001 2002 2003 2004 2005 Normalized Growth Rate ASIC/ASSP Logic Industrial Compared Growth Rates 1997 Index = 1.00 Development Costs Outpace End-Market Growth

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