Alex Tal 1

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Published on January 3, 2008

Author: demirel

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Overview of Silicon Implementation Methods:  Overview of Silicon Implementation Methods Alex Tal Ezchip Technologies Co-Founder, Former CTO Jun 2005 talalex@gmail.com Agenda:  Agenda The options Cell Based Gate Array Structured FPGA COT Case Study - EZchip The options :  The options The 4 basic alternatives to implement an IC system on a chip level design (SOC) today are cell based, gate array, structured, FPGA The prompt selection for a high end SOC is a cell based IC The cell based model could be either an ASIC vendor or COT Cell Based :  Cell Based A standard cell library - pre-tested and pre-characterized, ranges from simple gates, muxes , flip flops to memory blocks. The design netlist is layout on a die All the mask layers transistors and interconnect are customized and unique to a particular customer Advantages - The best solution in terms of area, performance and power Disadvantages - Long development cycle PD and manufacturing, high NRE, design risks (e.g logic, Physical Design, yield, Quality and reliability) Cell Based ASIC Vendor :  Cell Based ASIC Vendor The customer supplies synthesized gate level netlist to the ASIC vendor The ASIC vendor takes responsibility from gate level, performs back-end design and manufacturing. The NRE and unit price are negotiable with ASIC vendor ASIC vendor model contrasted to COT - Convenient, Lower NRE, Higher Chip Price, less risk (reliability, yield) Cell Based COT:  Cell Based COT COT model – The customer supplies GDSII format to the foundry The customer takes responsibility for manufacturing. A challenging design and logistic task High NRE costs – several design contractors, Layout tools, IP, Mask tooling, Wafers, Testing, Assembly, Shipment, Qualification and Characterization Low Chip Price – Direct control from design to manufacturing SOC advantage - could use the best IP available Gate Array:  Gate Array A predefined replicated pattern of a basic gate (a.k.a sea of gates) pre diffused on a silicon wafer but unconnected. Only few custom top layer metal masks are needed. The chip is completed during metal phase. Advantages – Fast production time, Relatively Low NRE, Relatively Low Cost Disadvantages – Larger area and lower performance as compared to cell based Still used in the far east Structured:  Structured FPGA offers fast development time and low development cost but high unit price. Cell Based ASIC offers low unit cost, but high cost of design and development Structured ASIC address the gap between these two approaches A predefined pre-placed platform of logic cells, embedded memory, IO and IP cores – largely pre fabricated on a silicon and configured in the fab. Typically 1-2 masks required for closure Each ASIC vendor has its own unique architecture. LSI Logic RapidChip, Altera HardCopy, ChipX Structured Conceptual Architecture:  Structured Conceptual Architecture Two Main Levels Structured Elements E.g R-cell configurable via metal to 200 library cells Array of Structured Elements Transistor fabric IP library e.g ARM, MAC Embedded memory Blocks Configurable I/O Structured Analysis:  Structured Analysis Advantages – Fast cycle time (e.g pre fabricated wafer banking), lower NRE, simplified design flow (a conventional ASIC handoff), reduced physical design risks (e.g pre-tested signal integrity, clock tree, supply grid), reduced yield risks Disadvantages – Need to select an ASIC vendor early, design might not fit, power management flexibility is limited, performance is lower and unit price is higher compared to cell based FPGA:  FPGA Field Programmable Gate Array A user programmable logic device configured in the field rather than in a fab. A variety of FPGA architectures on the market – e.g Xilinx, Altera Gate density at max 6 to 8 millions Advantages – Easy to design, Very low NRE, Rapid time to market, Fast TAT, minimal reliability risk Disadvantages – Design Size Limited and Complexity Limited, Performance limited, Power consumption, High Per Unit Cost, timing closure Design Security In FPGA:  Design Security In FPGA Issue – How to protect an IP implemented within FPGA ? In SRAM based FPGA external boot-up configuration PROM could be pirated - copied, reverse engineered, tampered Solution : use internal non volatile flash or anti-fuse which retain the configuration. Drawback expensive, limited density, anti-fuse programmed only once Another solution : Encrypted configuration bit-stream. FPGA stores the decryption key. The configuration file is encrypted. At system power up the FPGA decrypts the configuration COT Flow:  COT Flow RTL Design: Verilog, VHDL Syntesis: Gate level netlist Physical design: GDSII File Foundry: Mask, Wafer Production, PCM Wafer Probe Test Assembly/Package Final Test, Optional Burn In Shipment Preparations Delivery to the customer COT Yield:  COT Yield Wafer Processing Yield ASIC - ASIC Vendor COT - Foundry Design Yield ASIC - ASIC Vendor COT - Customer Few COT Challenges:  Few COT Challenges Engineering – balancing in-house vs. outsourcing IP – validated logic and physical, price and royalties Foundry– IDM vs Pure-Play, Capacity, Capability, Relationship, Price, Support Assembly and Test House – Capability, Geography, pricing, cycle time, relationship Qualification and characterization, yield optimization, failure analysis EZchip:  NP-1c Embedded search memory Embedded search memory EZchip From Link/ SF/ Host External Search Memory keys search results search results To Link/ SF/ Host TOP Search II Statistics Memory Four types of TOPs – Task Optimized Processors Each tailored for specific tasks Embedded search memories Embedded search memory Embedded frame memories Embedded search memory EZchip:  EZchip 10 Gigabit Network Processors Line Highly integrated array of Processors, Search Engines and Traffic Managers on a single chip Products – NP-1 sampled in Mar 2002 in IBM 0.18u [Cell Based, ASIC Vendor Model] NP-1c sampled in Apr 2003 in IBM 0.13u. In production since 12/2003 [Cell Based, ASIC Vendor Model] NP-2 samples in Jun 2005 in TSMC 0.13u [Cell Based COT Model] Full Custom:  Full Custom Some (or all) logic cells are customized and all mask layers are customized. The designer gives up using pre-tested and pre-characterized library cells The designer has total control over the size of every transistor forming every logic gate, so they can "fine tune" each gate for optimum performance, hand crafting Why to use: need a special IP, cell libraries not available, cell libraries are not fast enough, or not small enough or consume too much power The most expensive method to manufacture and design It is used primarily for devices such as high speed CPU produced in huge quantities. Another area is analog and mixed signal ICs

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