9 5 06 Trigger

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Information about 9 5 06 Trigger

Published on October 5, 2007

Author: Spencer

Source: authorstream.com

CSC Trigger News :  CSC Trigger News Dan Holmes University of Florida ( ) talk contents::  talk contents: Hardware Production & test status UF L1 trigger UCLA TPG UF L1 Readout hardware firmware MTCC Preparations hardware software CMSSW emulation Wesley’s requests UXC 55 integration latency Hardware Production & testing:  Hardware Production & testing Sector Processors (CMS needs 12) production of 21 completed Sept 05 19/21 pass tests 2 being reworked. SP Mezzanine Cards (CMS 12+1) produced 26 complete. all pass tests. DDU extender (CMS 1) production of 5 complete ongoing testing part of wider L1 trigger readout testing DT-CSC transition cards (CMS 12) production of 21 complete all now pass tests total of 5 now at CERN Production Status (Greg Rakness, UCLA):  Production Status (Greg Rakness, UCLA) Trigger Mother Boards (CMS = 468 + 15% spare) TPG part of trigger chain upstream of SP has been under an aggressive production schedule 550 produced boards at or en-route au CERN = 280 -> over half! CERN arrival schedule 480 by mid-July RPC-ALCT Transition Modules (CMS = 468 + 15% spare) passes RPC and ALCT data to TMB 540 produced boards at or en-route au CERN = 210 -> almost half... CERN arrival schedule 480 by mid-June Installation & commissioning of peripheral crates on yokes now replaces TPG hardware production as CSC critical path. CSC L1 trigger readout:  CSC L1 trigger readout Hardware: consists of SP --> DDU --> SLINK -->DAQ we have the path now set up in green barracks also ready is spy path of : DDU --> optical fiber --> local PC and also SP --> VME --> local PC In UF they have a parallel system (cosmic stand) which has all but the slink r/o path. Firmware: SP has new set: change in the trigger data format so that it is compatible with that expected by a standard EMu DDU. FMM should now follow the FSM as in; http://cmsdoc.cern.ch/cms/TRIDAS/horizontal/RUWG/DAQ_IF_guide/DAQ_IF_guide.html Trigger DDU also has new set: sets ‘source ID’ for s-link as 760 (dec) as required by DAQ First integration test with global DAQ scheduled for this afternoon! http://cern.ch/cms-emu-slicetest MTCC Preparations:  MTCC Preparations Hardware All hardware we necessary to fulfill our full MTCC deliverable is now installed at SX5/green barracks As of last week, all 36 chambers CSC expects to deliver are hooked up re-timing done, detector calibration this week, minor debugging of a few chambers (firmware, loose cables, etc.) Full DAQ readout all way to global DAQ, including trigger trigger readout still under development, Detector data readout well tested. New rack PCs installed, aliases of emutf and emuttc now moved to point at them. MTCC Preparations:  MTCC Preparations software (trigger only) Tagged release “APR_06” of TriDAS/trigger/csctf deployed on new PC. csctf/ts package is not included in release yet as there were problems of compatibility with new ts framework. I *think* as of this morning that we are back to where we were with ts. Will try it out at slice test this week, interact with the central cell..?! (ts) Services expected for MTCC: Khristian Khotov (UF) has been working on DB. We should be able to read/write our trigger configurations soon. ts package naturally provides a Hyperdaq and SOAP interface to our online software. Further DT-Phi LUTs now exist! ..result of 904 DT integration. Necessary for DT-CSC combined track finding in MTCC. CSC to DT trigger primitive ‘quality’ conversion scheme proposed. ..both results of 904 integration. Slide8:  CSC Track-Finder Emulator Status in CMSSW CSC Look Up tables ported. 100% match with ORCA Sector Processor Core logic ported. Need to add wrapper classes to connect SR LUTs to the SP. Need to port Pt-LUT algorithms to CMSSW Raw data processing already in place and working! L1 Tracks not stored into the event yet. Coming soon! Visualization for slicetest data already in place. Expect CSC Track Finder in CMSSW by the end of May. Waiting for CSC Trigger Primitive Generator! Slava Valuev (UCLA) plans to start before the end of May. CSC L1 trigger UXC 55 integration schedule:  CSC L1 trigger UXC 55 integration schedule The CSC L1 trigger consists of only one crate. We can move the hardware used in the MTCC to below ground once the MTCC is finished (ie September) It only really makes sense to move anything once services are available downstairs. network TTC clock stable (& well tested!!!) power and cooling Issues still pending: awaiting rack mount PC on order 9U CAEN on order alteration of back panel to allow exit of 72 DT link scsi cables latency (as given 11/11/05):  latency (as given 11/11/05) Chamber + Peripheral Crate:  Chamber + Peripheral Crate Chamber, CFEB, AFEB, ALCT MPC TMB/CLCT 14.5m cable 94m optical fibers SP 11m cables to GMT MS

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