7.digital design - programmable logic devices

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Information about 7.digital design - programmable logic devices
Design

Published on February 20, 2014

Author: mohamedaly71653

Source: slideshare.net

Digital design Programmable logic devices

Introduction  Facts: – It is most economical to produce an IC in large volumes – Many designs required only small volumes of ICs  Need an IC that can be: – Produced in large volumes – Handle many designs required in small volumes  A programmable logic part can be: – made in large volumes – programmed to implement large numbers of different low-volume designs

Why programmable logic?  Faster product time to market  Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environment  Most programmable logic devices are erasable and reprogrammable. – Allows “updating” a device or correction of errors – Allows reuse the device for a different design - the ultimate in re-usability! – Ideal for course laboratories  Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs. – Complete Intel Pentium designs were actually prototyped with specialized systems based on large numbers of VLSI programmable devices!

Programming technologies  Programming technologies are used to: – Control connections – Build lookup tables – Control transistor switching  The technologies – Control connections • Mask programming • Fuse • Anti-fuse • Single-bit storage element

Programming technologies(Cont.)  The technologies(Cont.) – Build lookup tables • Storage elements (as in a memory) – Transistor Switching Control • Stored charge on a floating transistor gate – Erasable – Electrically erasable – Flash (as in Flash Memory) • Storage elements (as in a memory)

Technology characteristics • Permanent - Cannot be erased and reprogrammed – Mask programming – Fuse – Anti-fuse • Reprogrammable – Volatile - Programming lost if chip power lost • Single-bit storage element – Non-Volatile • Erasable • Electrically erasable • Flash (as in Flash Memory) – Build lookup tables • Storage elements (as in a memory) – Transistor Switching Control • Stored charge on a floating transistor gate – Erasable – Electrically erasable – Flash (as in Flash Memory) • Storage elements (as in a memory)

Programmable logic arrays  Pre-fabricated building block of many AND/OR gates – Actually NOR or NAND – ”Personalized" by making or breaking connections among gates – Programmable array block diagram for sum of products form • • • inputs AND array product terms OR array outputs • • •

Programmable logic array(cont.) Before programming  All possible connections available before "programming" – In reality, all AND and OR gates are NANDs

Programmable logic array(cont.) After programming  Unwanted connections are "blown" – Fuse (normally connected, break unwanted ones) – Anti-fuse (normally disconnected, make wanted connections) A B C AB B'C AC' B'C' A F0 F1 F2 F3

Programmable logic array(cont.) Alternate representation for high fan-in structures  Short-hand notation-don't have to draw all the wires – Signifies a connection is present and perpendicular signal is an input to gate notation for implementing F0 = A B + A' B' F1 = C D' + C' D A B C D AB A'B' CD' C'D AB+A'B' CD'+C'D

Programmable logic array(cont.) Example  Multiple functions of A, B, C – – – – – – A 0 0 0 0 1 1 1 1 F1 = A B C F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C F6 = A xnor B xnor C B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F1 F2 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 F3 F4 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 F5 F6 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 A B C full decoder as for memory address bits stored in memory A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC F1 F2 F3 F4 F5 F6

Programmable array logic  Programmable array logic (PAL) – Constrained topology of the OR array – Innovation by Monolithic Memories – Faster and smaller OR plane a given column of the OR array has access to only a subset of the possible product terms

Read-only memories word lines (only one is active – decoder is just right for this)  Store permanent binary information  2n x m ROM – N address input lines – enable input(s) – three-state outputs  Two dimensional array of 1s and 0s – Entry (row) is called a "word" – Width of row = word-size – Index is called an "address" – Address is input – Selected word is output 1 1 1 1 n 2 -1 i decoder word[i] = 0011 j word[j] = 1010 0 0 n-1 Address bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) internal organization

Read-only memories(cont.) ROMs and combinational logic  Combinational logic implementation (twolevel canonical form) using a ROM F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F0 0 1 0 0 1 1 0 0 F1 0 1 1 0 0 0 0 1 F2 1 1 0 0 1 0 0 0 truth table F3 0 0 0 1 1 0 1 0 ROM 8 words x 4 bits/word A B C address F0 F1 F2 F3 outputs block diagram

ROM vs. PLA  ROM approach advantageous when – Design time is short (no need to minimize output functions) – Most input combinations are needed (e.g., code converters) – Little sharing of product terms among output functions  ROM problems – Size doubles for each additional input – Can't exploit don't cares  PLA approach advantageous when – Design tools are available for multi-output minimization – There are relatively few unique minterm combinations – Many minterms are shared among the output functions  PAL problems – Constrained fan-ins on OR plane

Regular logic structures for two-level logic  ROM – full AND plane, general OR plane – Cheap (high-volume component) – Can implement any function of n inputs – Medium speed  PAL – programmable AND plane, fixed OR plane – Intermediate cost – Can implement functions limited by number of terms – High speed (only one programmable plane that is much smaller than ROM's decoder)  PLA – programmable AND and OR planes – Most expensive (most complex in design, need more sophisticated tools) – Can implement any function up to a product term limit – Slow (two programmable planes)

Regular logic structures for multi-level logic  Difficult to devise a regular structure for arbitrary connections between a large set of different types of gates – Efficiency/speed concerns for such a structure – Xilinx field programmable gate arrays (FPGAs) are just such programmable multi-level structures • Programmable multiplexers for wiring • Lookup tables for logic functions (programming fills in the table) • Multi-purpose cells (utilization is the big issue)  Use multiple levels of PALs/PLAs/ROMs – Output intermediate result – Make it an input to be used in further logic

Sequential programmable logic devices  SPLD(Sequential Programmable Logic Devices)  CPLD(Complex Programmable Logic Device)  FPGA(Field Programmable Gate Array)

Sequential programmable logic devices(Cont.)  Flip-flops within the IC chip in addition to the AND-OR array – Field-Programmable Logic Sequencer (FPLS) • The FFs are flexible in that they can be programmed to operate as either JK or D type AND-OR array Flip-flop

Complex programmable logic device  Put a lot of PLDS on a chip  Add wires between them whose connections can be programmed PLD I/O Block PLD PLD Programmable switch matrix PLD PLD PLD I/O Block

Field programmable gate array  Emulate gate array technology  Hence Field Programmable Gate Array  You need: – A way to implement logic gates – A way to connect them together  PALs, PLAs = 10 - 100 Gate Equivalents  Field Programmable Gate Arrays = FPGAs – 100 - 1000(s) of Gate Equivalents

Field programmable gate array(Cont.) Structure of FPGA  Logic blocks – To implement combinational and sequential logic  Interconnect – Wires to connect inputs and outputs to logic blocks  I/O blocks – Special logic blocks at periphery of device for external connections  Key questions: – How to make logic blocks programmable? – How to connect the wires? – After the chip has been fabbed

Field programmable gate array(Cont.) Interconnect  Problem: – Thousands of operators producing results – Each taking as outputs the results of other bit operators – Initial assumptions – have to connect them all simultaneously Processing units Interconnect Input/output Interconnect area, delay and power.

Field programmable gate array(Cont.) Basic I/O block structure D EC Three-State FF Enable Clock Q Three-State Control SR Set/Reset D EC Output FF Enable SR Q Output Path Direct Input FF Enable Registered Input Q D EC SR Input Path

Field programmable gate array(Cont.) I/O block functionality  IOB provides interface between the package pins and CLBs  Each IOB can work as uni- or bi-directional I/O  Outputs can be forced into High Impedance  Inputs and outputs can be registered – advised for high-performance I/O  Inputs can be delayed

thanks digital design

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