Published on February 20, 2014
Digital design Memory basics
Definitions Memory is a collection of storage cells together with associated circuits needed to transfer information into and out of these cells. Memory Interfaces for Accessing Data Asynchronous (un-clocked): A change in the address results in data appearing Synchronous (clocked): A change in address, followed by an edge on CLK results in data appearing or write operation occurring. A common arrangement is to have synchronous write operations and asynchronous read operations. Volatile: Looses its state when the power goes off. Nonvolatile: Retains it state when power goes off.
Basic memory system block diagram Word Line Address Decoder n Address Bits Memory cell m Bit Lines RAM/ROM naming convention: 32 X 8, "32 by 8" => 32 8-bit words 1M X 1, "1 meg by 1" => 1M 1-bit words 2n word lines what happens if n and/or m is very large?
Memory component types memories RAM Non volatile Volatile SRAM ROM DRAM NVRAM BRAM Non programmable FRAM One time programmable ROM OTP Programmable several times EPROM EEPROM Flash
Memory component types(Cont.) memories Read-write memory Read-only memory(ROM) Non-volatile volatile Random access SRAM Non-random access DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
SRAM memories Read-write memory Read-only memory(ROM) Non-volatile volatile Non-random access Random access SRAM DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
SRAM(Cont.) Static RAM cell 6-Transistor SRAM Cell 0 0 bit word word (row select) 1 1 bit Read: bit – 1. Select row – 2. Cell pulls one line low and one high – 3. Sense output on bit and bit replaced with pullup Write: – 1. Drive bit lines (e.g, bit=1, bit=0) – 2. Select row bit to save area Why does this work? When one bit-line is low, it will force output high; that will set new state
SRAM(Cont.) Typical SRAM organization: 16-word x 4-bit Din 3 Din 2 Din 1 Din 0 Wr Driver + Wr Driver + Wr Driver + Wr Driver + SRAM Cell : SRAM Cell - Sense Amp + Dout 3 SRAM Cell SRAM Cell : SRAM Cell - Sense Amp + Dout 2 SRAM Cell SRAM Cell : SRAM Cell - Sense Amp + Dout 1 Word 0 SRAM Cell SRAM Cell Word 1 : Word 15 SRAM Cell - Sense Amp + Dout 0 Address Decoder SRAM Cell WrEn A0 A1 A2 A3
SRAM(Cont.) Simplified SRAM timing diagram Read: Valid address, then Chip Select Access Time: address good to data valid – even if not visible on out Cycle Time: min between subsequent mem operations Write: Valid address and data with WE_l, then CS – Address must be stable a setup time before WE and CS go low – And hold time after one goes high When do you drive, sample, or Z the data bus?
SRAM(Cont.) Logic diagram of a typical SRAM A N WE_L OE_L 2 N“words” x M bit SRAM M Write Enable is usually active low (WE_L) Din and Dout are combined to save pins: A new control signal, Output Enable (OE_L) – WE_L is asserted (Low), OE_L is unasserted (High) • D serves as the data input pin – WE_L is unasserted (High), OE_L is asserted (Low) • D is the data output pin – Neither WE_L and OE_L are asserted? or chipSelect (CS) + WE • Chip is disconnected – Never both asserted! D
SRAM(Cont.) Typical SRAM timing A N WE_L OE_L OE determines direction Hi = Write, Lo = Read Writes are dangerous! Be careful! Double signaling: OE Hi, WE Lo 2 N words x M bit SRAM M D Write Timing: D Data In A Read Timing: High Z Write Address Data Out Junk Read Address Data Out Read Address OE_L WE_L Write Hold Time Write Setup Time Read Access Time Read Access Time
SRAM(Cont.) Synchronous SRAM
SRAM(Cont.) What happens when # bits gets large Big slow decoder Bit lines very log Log n bit address n bits Row decoder – Large distributed RC load Treat output as differential signal, rather than rail-to-rail logic – Sense amps on puts – Can ‘precharge’ both bit lines high, so cell only has to pull one low ==> Make it shorter and wider
SRAM(Cont.) Log k bit address Row decoder Inside a tall-thin RAM is a short-fat RAM n = k x m bits Sense amps Column mux Log m bit address 1 data bit Controls physical aspect ratio – Important for physical layout and to control delay on wires.
SRAM(Cont.) Larger/Wider memories Made up from sets of chips Consider a 64K by 8 RAM How to design a 256K x 8 RAM using a 64K by 8 RAM? How many address lines in total?
SRAM(Cont.) Larger/Wider memories(Cont.) Larger memory 256K X 8 Connect all output data lines together (tristate) Connect all input data line together 16 lines of address to fetch a word in any RAM chip How to select the specific RAM chip?
SRAM(Cont.) Larger/Wider memories(Cont.) Larger memory(Cont.) Decoder for highorder 2 bits -Selects chip -Look at selection logic -Address ranges 17
SRAM(Cont.) Larger/Wider memories(Cont.) Wider memory How to design a 64K X 16 RAM using a 64K X 8 RAM?
SRAM(Cont.) Problems with SRAM Six transistors use up lots of area Consider a “Zero” is stored in the cell: – Transistor N1 will try to pull “bit” to 0 – Transistor P2 will try to pull “bit bar” to 1 If Bit lines are pre-charged high: are P1 and P2 really necessary? – Read starts by precharging bit and ~bit – Selected cell pulls one of them low – Sense the difference Select = 1 P1 P2 Off On On bit = 1 On On Off N1 N2 bit = 0
DRAM memories Read-write memory Read-only memory(ROM) Non-volatile volatile Non-random access Random access SRAM DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
DRAM(Cont.) Select T B Stored 0 Stored 1 To Pump C DRAM cell (b) (a) (c) Write 1 Write 0 Select B D Q C C (d) (e) Read 1 Read 0 DRAM cell model (h) (f) (g)
DRAM(Cont.) 1-Transistor memory cell Write: – 1. Drive bit line – 2. Select row Read: – 1. Precharge bit line to Vdd/2 – 2. Select row – 3. Cell and bit line share charges • Minute voltage changes on the bit line – 4. Sense (fancy sense amp) • Can detect changes of ~1 million electrons – 5. Write: restore the value Refresh – 1. Just do a dummy read to every cell. row select bit Read is really a read followed by a restoring write
DRAM(Cont.) Destructive read Vdd sense amp bitline voltage 1 0 Wordline Enabled Sense Amp Enabled After read of 0 or 1, cell contains something close to Vdd/2 Vdd storage cell voltage
DRAM(Cont.) Refresh So after a read, the contents of the DRAM cell are gone The values are stored in buffer Write them back into the cells for the next read in the future DRAM cells Sense Amps Buffer
DRAM(Cont.) Refresh(Cont.) Fairly gradually, the DRAM cell will lose its contents even if it’s not accessed – This is why it’s called “dynamic” – Contrast to SRAM which is “static” in that once written, it maintains its value forever (so long as power remains on) All DRAM rows need to be regularly read and re-written 1 0 Gate Leakage
DRAM(Cont.) Classical DRAM organization(Square) bit (data) lines r o w d e c o d e r row address Each intersection represents a 1-T DRAM Cell RAM Cell Array Square keeps the wires short: Power and speed advantages Less RC, faster precharge and discharge is faster access time! word (row) select Column Selector & I/O Circuits data Column Address Row and Column Address together select 1 bit a time
DRAM(Cont.) DRAM Logical organization(4 Mbit) 4 Mbit = 22 address bits 11 row address bits 11 col address bits Column Decoder … Sense Amps & I/O 11 A0…A10 D E C O D E R 11 Bit line R O W Memory Array (2,048 x 2,048) Storage Word Line Cell Square root of bits per RAS/CAS – Row selects 1 row of 2048 bits from 2048 rows – Col selects 1 bit out of 2048 bits in such a row D Q
DRAM(Cont.) DRAM with column buffer R O W A0…A10 D E C O D E R … 11 Memory Array (2,048 x 2,048) Storage Word Line Cell Sense Amps Column Latches MUX Pull column into fast buffer storage Access sequence of bit from there
DRAM(Cont.) Logic diagram of a typical DRAM RAS_L A 9 CAS_L WE_L 256K x 8 DRAM OE_L 8 D Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low Din and Dout are combined (D): – WE_L is asserted (Low), OE_L is disasserted (High) • D serves as the data input pin – WE_L is disasserted (High), OE_L is asserted (Low) • D is the data output pin Row and column addresses share the same pins (A) – RAS_L goes low: Pins A are latched in as row address – CAS_L goes low: Pins A are latched in as column address – RAS/CAS edge-sensitive
DRAM(Cont.) DRAM read timing RAS_L Every DRAM access begins at: – – Assertion of the RAS_L 2 ways to read: early or late v. CAS CAS_L WE_L A 256K x 8 DRAM 9 OE_L D 8 DRAM Read Cycle Time RAS_L CAS_L A Row Address Col Address Junk Row Address Col Address Junk WE_L OE_L D High Z Junk Data Out Read Access Time Early Read Cycle: OE_L asserted before CAS_L High Z Data Out Output Enable Delay Late Read Cycle: OE_L asserted after CAS_L
DRAM(Cont.) Early read sequencing Assert Row Address Assert RAS_L – Commence read cycle – Meet Row Addr setup time before RAS/hold time after RAS Assert OE_L Assert Col Address Assert CAS_L – Meet Col Addr setup time before CAS/hold time after CAS Valid Data Out after access time Disassert OE_L, CAS_L, RAS_L to end cycle
DRAM(Cont.) Sketch of early read FSM FSM Clock? Row Address to Memory Setup time met? Assert RAS_L Hold time met? Assert OE_L, RAS_L Col Address to Memory Setup time met? Assert OE_L, RAS_L, CAS_L Hold time met? Assert OE_L, RAS_L, CAS_L Data Available (better grab it!)
DRAM(Cont.) Late read sequencing Assert Row Address Assert RAS_L – Commence read cycle – Meet Row Addr setup time before RAS/hold time after RAS Assert Col Address Assert CAS_L – Meet Col Addr setup time before CAS/hold time after CAS Assert OE_L Valid Data Out after access time Disassert OE_L, CAS_L, RAS_L to end cycle
DRAM(Cont.) Sketch of late read FSM FSM Clock? Row Address to Memory Setup time met? Assert RAS_L Hold time met? Col Address to Memory Assert RAS_L Setup time met? Col Address to Memory Assert RAS_L, CAS_L Hold time met? Assert OE_L, RAS_L, CAS_L Data Available (better grab it!)
DRAM(Cont.) DRAM write timing RAS_L CAS_L WE_L OE_L Every DRAM access begins at: – – The assertion of the RAS_L 2 ways to write: early or late v. CAS A 256K x 8 DRAM 9 8 Col Address Junk D DRAM WR Cycle Time RAS_L CAS_L A Row Address Col Address Junk Row Address OE_L WE_L D Junk Data In WR Access Time Early Wr Cycle: WE_L asserted before CAS_L Junk Data In Junk WR Access Time Late Wr Cycle: WE_L asserted after CAS_L
DRAM(Cont.) Key DRAM timing parameters tRAC: minimum time from RAS line falling to the valid data output. – Quoted as the speed of a DRAM – A fast 4Mb DRAM tRAC = 60 ns tRC: minimum time from the start of one row access to the start of the next. – tRC = 110 ns for a 4Mbit DRAM with a tRAC of 60 ns tCAC: minimum time from CAS line falling to valid data output. – 15 ns for a 4Mbit DRAM with a tRAC of 60 ns tPC: minimum time from the start of one column access to the start of the next. – 35 ns for a 4Mbit DRAM with a tRAC of 60 ns
DRAM(Cont.) Improved DRAM schemes Often want to access a sequence of bits Fast Page mode – After RAS / CAS, can access additional bits in the row by changing column address and strobing CAS Static Column mode – Change column address (without repeated CAS) to get different bit Nibble mode – Pulsing CAS gives next bit mod 4 Video ram – Serial access
DRAM(Cont.) Improved DRAM schemes(Cont.) EDO - extended data out (similar to fast-page mode) – RAS cycle fetched rows of data from cell array blocks (long access time, around 100ns) – Subsequent CAS cycles quickly access data from row buffers if within an address page (page is around 256 Bytes) SDRAM - synchronous DRAM – clocked interface – uses dual banks internally. Start access in one bank then next, then receive data from first then second. DDR - Double data rate SDRAM – Uses both rising (positive edge) and falling (negative) edge of clock for data transfer. (typical 100MHz clock with 200 MHz transfer). RDRAM - Rambus DRAM – Entire data blocks are access and transferred out on a high-speed buslike interface (500 MB/s, 1.6 GB/s) – Tricky system level design. More expensive memory chips.
DRAM(Cont.) Improved DRAM schemes(Cont.) Fast Page Mode DRAM(FPM DRAM) – Multiple accesses to different columns from same row – Saves RAS and RAS to CAS delay RAS CAS A X Row X Col n X Col n+1 X Data n Data X Col n+2 D n+1 D n+2 Extended Data Output RAM (EDO RAM) – A data output latch enables to parallel next column address with current column data RAS CAS A Data X Row X Col n X Col n+1 X X Col n+2 Data n Data n+1 Data n+2
DRAM(Cont.) Improved DRAM schemes(Cont.) Burst DRAM – Generates consecutive column address by itself RAS CAS A[ Data X Row X Col n X Data n Data n+1 Data n+2
DRAM(Cont.) Improved DRAM schemes(Cont.) Synchronous DRAM (SDRAM) -All signals are referenced to an external clock Makes timing more precise with other system devices -Multiple Banks Multiple pages open simultaneously (one per bank) -Command driven functionality instead of signal driven ACTIVE: selects both the bank and the row to be activated • ACTIVE to a new bank can be issued while accessing current bank READ/WRITE: select column -Read and write accesses to the SDRAM are burst oriented Successive column locations accessed in the given row Burst length is programmable: 1, 2, 4, 8, and full-page • May end full-page burst by BURST TERMINATE to get arbitrary burst length -A user programmable Mode Register CAS latency, burst length, burst type -Auto pre-charge: may close row at last read/write in burst -Auto refresh: internal counters generate refresh address
DRAM(Cont.) Improved DRAM schemes(Cont.) cmd ACT NOP t RCD > 20ns RD RD+PC ACT NOP RD ACT NOP RD NOP NOP NOP t RRD > 20ns t RC>70ns BL = 1 Bank Bank 0 X Bank 0 Bank 0 Bank 1 X Bank 1 Bank 0 X Bank 0 X X X Addr Row i X Col j Col k Row m X Col n Row l X Col q X X X CL=2 Data Data j Data k Data n Data q tRCD: ACTIVE to READ/WRITE gap = tRCD(MIN) / clock period tRC: successive ACTIVE to a different row in the same bank tRRD: successive ACTIVE commands to different banks SDRAM timing clock
DRAM(Cont.) Synchronous DRAM Functional Block Diagram 8 Meg x 16 SDRAM 43
DRAM(Cont.) SDRAM details Multiple “banks” of cell arrays are used to reduce access time: – Commands are sent using the RAS, CAS, CS, & WE pins. – During RAS operation, address lines select the bank and row During CAS operation, address lines select the column. transfers the contents of the entire to a row buffer Subsequent “READ” or “WRITE” commands modify the contents of the row buffer. For burst reads and writes during “READ” or “WRITE” the starting address of the block is supplied. – Address pins are “time multiplexed” – “ACTIVE” command “opens” a row for operation – Each bank is 4K rows by 512 “columns” by 16 bits (for our part) Read and Write operations as split into RAS (row access) followed by CAS (column access) These operations are controlled by sending commands – Burst length is programmable as 1, 2, 4, 8 or a “full page” (entire row) with a burst terminate option. Special commands are used for initialization (burst options etc.) A burst operation takes 4 + n cycles (for n words)
DRAM(Cont.) Read burst(with auto pre-charge)
DRAM(Cont.) Write burst(with auto pre-charge) See datasheet for more details. Verilog simulation models available.
DRAM(Cont.) DRAM recap General Characteristics – Optimized for high density and therefore low cost/bit – Special fabrication process – DRAM rarely merged with logic circuits. – Needs periodic refresh (in most applications) – Relatively slow because: • High capacity leads to large cell arrays with high word- and bit-line capacitance • Complex read/write cycle. Read needs “precharge” and write-back word line DRAM bit cell bit line – Multiple clock cycles per read or write access – Multiple reads and writes are often grouped together to amortize overhead. Referred to as “bursting”.
DRAM(Cont.) DRAM performance Cycle Time Access Time Time DRAM (Read/Write) Cycle Time >> DRAM (Read/Write) Access Time – - 2:1; why? DRAM (Read/Write) Cycle Time : – How frequent can you initiate an access? – Analogy: A little kid can only ask his father for money on Saturday DRAM (Read/Write) Access Time: – How quickly will you get what you want once you initiate an access? – Analogy: As soon as he asks, his father will give him the money DRAM Bandwidth Limitation analogy: – What happens if he runs out of money on Wednesday?
DRAM(Cont.) DRAM performance(Cont.) cpu cpu cpu multiplexor cache cache memory memory Simple: cache memory module Wide: • CPU/Mux 1 word; Mux/Cache, Bus, Memory N words (Alpha: 64 bits & 256 bits) • CPU, Cache, Bus, Memory same width (32 bits) memory module memory module memory module Interleaved: • CPU, Cache, Bus 1 word: Memory N Modules (4 Modules); example is word interleaved
DRAM(Cont.) DRAM performance(Cont.) Increasing bandwidth - Interleaving Access Pattern without Interleaving: CPU Memory D1 available Start Access for D1 Start Access for D2 Memory Bank 0 Access Pattern with 4-way Interleaving: CPU Memory Bank 1 Access Bank 0 Memory Bank 2 Memory Bank 3 Access Bank 1 Access Bank 2 Access Bank 3 We can Access Bank 0 again
DRAM(Cont.) DRAM performance(Cont.) Timing model – 1 to send address, – 4 for access time, 10 cycle time, 1 to send data – Cache Block is 4 words Simple M.P. = 4 x (1+10+1) = 48 Wide M.P. = 1 + 10 + 1 = 12 Interleaved M.P. = 1+10+1 + 3 =15 address address address address 0 4 8 12 1 5 9 13 2 6 10 14 3 7 11 15 Bank 0 Bank 1 Bank 2 Bank 3
SRAM vs. DRAM The primary difference between different memory types is the bit cell. SRAM Cell DRAM Cell addr bit line word line word line data bit line Larger cell lower density, higher cost/bit No dissipation Read non-destructive No refresh required Simple read faster access Standard IC process natural for integration with logic bit line Smaller cell higher density, lower cost/bit Needs periodic refresh, and refresh after read Complex read longer access time Special IC process difficult to integrate with logic circuits Density impacts addressing
SRAM vs. DRAM(Cont.) • Random Access: access time is the same for all locations DRAM – Dynamic RAM SRAM – Static RAM Refresh Regular refresh (~1% time) No refresh needed Access Not true “Random Access” True “Random Access” density High (1 Transistor/bit) Low (6 Transistor/bit) Power low high Speed slow fast Price/bit low high Typical usage Main memory cache
Multi-ported memory Motivation: – Consider CPU core register file: • 1 read or write per cycle limits processor performance. • Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile. • Common arrangement in pipelined CPUs is 2 read ports and 1 write port. dataa sela selb selc Regfile datab datac
Dual-ported memory internals Add decoder, another set of read/write logic, bits lines, word lines: deca decb Example cell: SRAM Repeat everything but crosscoupled inverters. This scheme extends up to a couple more ports, then need to add additional transistors. cell array WL2 WL1 r/w logic r/w logic address ports data ports b2 b1 b1 b2
FIFO memories Read-write memory Read-only memory(ROM) Non-volatile volatile Random access SRAM Non-random access DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
FIFO(Cont.) First-In-First-Out memory Used to implement queues. These find common use in computers and communication circuits. Generally, used for rate matching data producer and consumer: stating state after write after read Producer can perform many writes without consumer performing any reads (or vice versa). However, because of finite buffer size, on average, need equal number of reads and writes. Typical uses: – interfacing I/O devices. Example network interface. Data bursts from network, then processor bursts to memory buffer (or reads one word at a time from interface). Operations not synchronized. – Example: Audio output. Processor produces output samples in bursts (during process swap-in time). Audio DAC clocks it out at constant sample rate.
FIFO(Cont.) FIFO interfaces DIN RST WE FULL HALF FULL EMPTY RE DOUT CLK FIFO After write or read operation, FULL and EMPTY indicate status of buffer. Used by external logic to control own reading from or writing to the buffer. FIFO resets to EMPTY state. HALF FULL (or other indicator of partial fullness) is optional. Address pointers are used internally to keep next write position and next read position into a dual-port memory. write ptr read ptr If pointers equal after write FULL: write ptr read ptr If pointers equal after read EMPTY: write ptr read ptr
Mask-programmed devices memories Read-write memory Read-only memory(ROM) Non-volatile volatile Random access SRAM Non-random access DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
Mask-Programmed devices(Cont.) Simplified form of memory. No write operation needed. Functional Equivalence: Connections to Vdd used to store a logic 1, connections to GND for storing logic 0. address decoder bit-cell array Full tri-state buffers are not needed at each cell point. In practice, single transistors are used to implement zero cells. Logic one’s are derived through precharging or bit-line pullup transistor.
Mask-Programmed devices(Cont.) The entire ROM consists of a number of row (word) and column (data) lines forming an array. Each column has a single pull-up resistor attempting to hold that column to a weak logic 1 value. Every row-column intersection has an associated transistor and, potentially, a mask-programmed connection. Logic 1 Mask-programmed connection Pull-up resistor Row (word) line Transistor Logic 0 Column (data) line
Mask-Programmed devices(Cont.) ROM as AND/OR logic device
One time programmable memories RAM Non volatile Volatile SRAM ROM DRAM NVRAM BRAM Non programmable FRAM One time programmable ROM OTP Programmable several times EPROM EEPROM Flash
One time programmable(Cont.) Fusible-Link based PROM The problem with mask-programmed devices is that creating them is a very expensive unless you intend to produce them in large quantities. Programmable ROM(PROM): It can be programmed (written to) only once via a PROM programmer For this reason, the first programmable read-only memory (PROM) devices were developed at Harris Semiconductor in 1970. Logic 1 Fusible link Pull-up resistor Row (word) line Transistor Logic 0 Column (data) line
EPROM memories Read-write memory Read-only memory(ROM) Non-volatile volatile Random access SRAM Non-random access DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
EPROM(Cont.) EPROM: Erasable Programmable ROM – The first device – the 1702 – introduced by Intel in 1971. – It can be erased with an ultraviolet light and then rewritten via a EPROM programmer
EPROM(Cont.) Standard MOS vs. EPROM transistor An EPROM transistor has the same basic structure as a standard MOS transistor, but with the addition of a second poly-silicon floating gate isolated by layers of oxide. Source Source terminal terminal Control gate Control gate terminal terminal Drain Drain terminal terminal Source Source terminal terminal Control gate Control gate terminal terminal Drain Drain terminal terminal control gate control gate control control gate gate source source drain drain (a) Standard MOS transistor (a) Standard MOS transistor Silicon Silicon dioxide dioxide Silicon Silicon substrate substrate floating gate floating gate source source drain drain (b) EPROM transistor (b) EPROM transistor
EPROM(Cont.) The Floating-gate transistor(FAMOS) Floating gate Gate Source D Drain G tox tox n+ p n +_ S Substrate Device cross-section Schematic symbol
EPROM(Cont.) Floating gate transistor(Cont.) Vt is pushed from 0.7 volts towards 5-7 Volts. So transistor will be off unless it is reprogrammed again. Ids Vgs
EPROM(Cont.) Floating gate transistor(Cont.)
EPROM(Cont.) Programming/Erasing Programming: apply a high voltage typically (10V – 25V) for a specified amount of time (typically 50 ms per address) and this requires a special programming circuit. -This will usually trap electrons in floating gate and program the bit to a ‘0’ value. Erasing: expose the EPROM to UV light, this will force the electrons trapped (due to application of high voltage) back to silicon substrate. -This will usually take 15-20 minutes -It will erase the entire chip
EPROM(Cont.) Transistor-based memory cell In its un-programmed state, all the floating gates in the EPROM transistors are uncharged. In this case, placing a row line in its active state will turn on all of the transistors and column lines are pulled to logic “0”. Logic 1 Pull-up resistor Row (word) line EPROM Transistor Logic 0 Column (data) line
EPROM(Cont.) Transistor-based memory cell(Cont.) As they are order of magnitude smaller than fusible links, EPROM cells are efficient in terms of silicon real estate. An EPROM device is delivered in a ceramic or plastic package with a small quartz window in the top. The main problem with EPROM devices are -Their expensive packages with quartz window and -The time it takes to erase it which is in the order of 20 minutes. -To program the device or erase it, a programmer has to remove the device from the receive circuit board and put onto a special programming device. -As the structures on the device become smaller and the density increases, a larger percentage of the surface of the die is covered by metal. This make it difficult for the EPROM cell to absorb UV light and increases the required exposure time.
EEPROM memories Read-write memory Read-only memory(ROM) Non-volatile volatile Random access SRAM Non-random access DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
EEPROM(Cont.) EEPROM (Electrically Erasable PROM) overcomes the limitations of the PROM by electrically programming and erasing the chip onboard. The structure looks similar to the floating gate EPROM (FAMOS transistor, floating gate avalanche transistor) with some minor modifications (FLOTOX transistor) the insulating oxide layers surrounding this gate are very much thinner. 1. Programming: involves applying a high voltage 2. Erasing: involves applying a reverse high voltage which causes a removal of trapped charge (tunneling)
EEPROM(Cont.) FLOTOX transistor Gate Floating gate Drain Source 20–30 nm n1 n1 Substrate p 10 nm FLOTOX transistor Fowler-Nordheim
EEPROM(Cont.) Transistor-based memory cell 2 transistor cell WL VDD BL A second transistor is used to select cell for erasure. • Advantages: electrically erase bytes in circuit Disadvantages: less dense than EPROM Normal MOS transistor E2PROM Cell E2PROM transistor
FLASH memories Read-write memory Read-only memory(ROM) Non-volatile volatile Random access SRAM Non-random access DRAM FIFO EPROM LIFO Maskprogrammed EEPROM Flash
FLASH(Cont.) The FLASH traces its ancestry to both the EPROM and EEPROM technologies (introduced in 1984/1988) The name “FLASH” was originally coined to reflect this technology’s rapid erasure times compared to EPROM. FLASH employs a variety of architectures. -Some have a single floating gate transistor cell with the same area as an EPROM cell, but with the thinner oxide layers characteristic of an EEPROM. These devices can be electrically erased, but only by clearing whole device or large portions. -Other architectures features a two-transistor cell similar to that of an EEPROM cell, thereby allowing them to be erased and reprogrammed on a word-by-word basis.
FLASH(Cont.) Control gate Floating gate erasure n 1 source Thin tunneling oxide programming p- substrate Many other options … n 1 drain
Comparison Memory type Density Speed Size Cost Volatility DRAM V.High Slow Small V. Cheap Y SRAM Low V. fast Large Costly Y ROM High fast Small Cheap N PROM High fast moderate Cheap N EPROM High V. Slow Small Cheap N EEPROM Medium V. Slow Moderate Cheap N Flash High V. Slow Small Cheap N
Read more about memories Ferroelectirc RAM(FcRAM) Resistance RAM Phase change RAM(PcRAM)
Relationship between memory and CL Memory blocks can be (and often are) used to implement combinational logic functions: Examples: – LUTs in FPGAs – 1Mbit x 8 EPROM can implement 8 independent functions each of log2(1M)=20 inputs. The decoder part of a memory block can be considered a “minterm generator”. The cell array part of a memory block can be considered an OR function over a subset of rows. The combination gives us a way to implement logic functions directly in sum of products form. Several variations on this theme exist in a set of devices called Programmable logic devices (PLDs)
How to use memories in design of sequential circuits?
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