Published on February 20, 2014
Digital design Timing analysis and performance measures
Element of Time +3 Propagation delay Vout 0 T • Logical change is not instantaneous • Broader digital design methodology has to make it appears as such – Clocking, delay estimation, glitch avoidance
Timing Methodologies Rules for interconnecting components and clocks – Guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements – Focus on systems with edge-triggered flip-flops • Found in programmable logic devices – Many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: – Correct inputs, with respect to time, are provided to the flipflops – No flip-flop changes state more than once per clocking event
Timing Methodologies (cont.) Definition of terms – clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level – setup time: minimum time before the clocking event by which the input must be stable (Tsu) – hold time: minimum time after the clocking event until which the input must remain stable (Th) Tsu Th data D Q input clock there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized clock stable changing data clock D Q
Typical Timing Specifications Positive edge-triggered D flip-flop – Setup and hold times – Minimum clock width – Propagation delays (low to high, high to low, max and typical) D CLK Q Tsu Th 20ns 5ns Tsu 20ns Th 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns all measurements are made from the clocking event that is, the rising edge of the clock
Cascading Edge-triggered Flip-Flops Shift register – New value goes into first stage – While previous value of first stage goes into second stage – Consider setup/hold/propagation delays (prop must be > hold) IN D Q Q0 D Q CLK Q1 OUT 100 IN Q0 Q1 CLK
Cascading Edge-triggered Flip-Flops (cont.) Why this works – Propagation delays exceed hold times – Clock width constraint exceeds setup time – This guarantees following stage will latch current value before it changes to new value In Q0 Tsu 4ns Tsu 4ns Tp 3ns Q1 Tp 3ns timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the clock CLK Th 2ns Th 2ns
Timing constraints FF1 din D clock C Q A combinational logic B FF2 D Q C Let’s assume that din is applied in a way that satisfies setup and hold for FF1, and let’s examine what will happen at FF2 dout
Timing constraints(Cont.) FF1 din D clock C Tclock tP A Q tFF1 combinational logic B FF2 D Q dout C Tsu2 Th2 clock din A B tFF1 Setup constraint tP tFF1 + tP < Tclock – Tsu2 tFF1 tP tFF1 + tP > Th2 Hold constraint
Max/Min delays FF1 din clock Setup constraint D C tP A Q tFF1 combinational logic tFF1 + tP < Tclock – Tsu2 B FF2 D Q dout C tFF1 + tP > Th2 Hold constraint Unfortunately, delays through gates are not constant. Delays change with: – Supply Voltage, Temperature, and Manufacturing Process Setup constraint is more difficult to satisfy when delays are max (V , T , P ) Hold constraint is more difficult to satisfy when delays are min (V , T , P ) i + v - dv iC dt for i constant: if dv decreases, dt must increases
Minimum Clock period
Clock Non-idealities Clock skew – Spatial variation in temporally equivalent clock edges; deterministic + random, tSK Clock jitter – Temporal variations in consecutive edges of the clock signal; modulation + random noise – Cycle-to-cycle (short-term) tJS – Long term tJL Variation of the pulse width – Usually not important in register-based clocking
Clock Uncertainties 4 Power Supply 3 Interconnect Devices Variation 2 5 Temperature 1 Clock Generation Sources of clock uncertainty 6 Capacitive Load 7 Coupling to Adjacent Lines
Clock skew In this example if clock0=clock1 (no skew) setup at FF2 is violated tP FF1 din D clock Q C tFF1 tskew clock0 FF2 D Q dout C skew clock0 tskew combinational logic B = clock clock1 Positive skew makes easier to satisfy setup constraint: tFF1+tP < Tclock–Tsu2+tskew clock1 T(0)h din T(0) su Tsu2 Th2 Positive skew makes more difficult to satisfy hold constraint: tFF1 + tP > Th2+tskew B tFF1 + tP
Timing performance measures units definition delay clock period T clock frequency time from pointpoint rising edge rising edge of clock 1 ns ns MHz clock period latency time from inputoutput throughput #output bits/time unit ns Mbits/s
Latency input top-level entity 8 bits 8 bits D Q Combinational Logic clk D Combinational Logic Q D clk Q output clk 100 MHz clk input(0) input i.e. time it takes from first input to first output, second input to second output, etc. Latency is usually constant for a system (but not always) Also called input-to-output latency Count the number of rising edges of the clock! – output(0) Latency is the time between input(n) and output(n) – – – input(2) (unknown) output input(1) In this example, 3 rising edges from input to output latency is 3 cycles Latency is measured in clock cycles (then translated to seconds) – In this example, say clock period is 10 ns, then latency is 30 ns output(1)
Throughput input top-level entity 8 bits 8 bits D Q Combinational Logic clk D Q Combinational Logic D clk output Q clk clk input output • (unknown) input(2) output(0) output(1) 1 cycle betweeen output samples In this example, 8 bits per output sample Time between consecutive output samples: clock cycles between output(n) to output(n+1) – – input(1) Throughput = (bits per output sample) / (time between consecutive output samples) Bits per output sample: – input(0) Can be measured in clock cycles, then translated to time In this example, time between consecutive output samples = 1 clock cycle = 10 ns Throughput = (8 bits per output sample) / (10 ns) = 0.8 bits / ns = 800 Mbits/s
Pipelining D Q Combinational Logic clk D Q clk tLOGIC = 10 ns Assuming tCLK2Q = tS = 0 ns, the critical path is 10 ns, and the maximum clock frequency is 100 MHz – Latency = 2 cycles
Pipelining(Cont.) Combinational Logic register splits logic in half D Q Combinational Logic A clk D Q Q clk clk tLOGICA = 5 ns D Combinational Logic A tLOGICB = 5 ns Purpose of pipelining is to reduce the critical path of the circuit by inserting an additional register (called a pipeline register) – This splits the combinational logic in half Now critical path delay is 5 ns, so maximum clock frequency is 200 MHz – Double the clock frequency However, latency increases to 3 cycles (and area is increased due to additional register) In general, pipelining increases throughput at the cost of increased latency and area/power
Time multiplexing and parallelism
Time multiplexing and parallelism
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