3.digital design - electronics refresher and technology parameters

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Information about 3.digital design - electronics refresher and technology parameters

Published on February 20, 2014

Author: mohamedaly71653

Source: slideshare.net

Digital design Electronics refresher and technology parameters

Semiconductor essentials: properties  Metallic conductor:  Typically 1 or 2 freely moving electrons per atom  Semiconductor:  Typically 1 freely moving electron per 1091017 atoms

Semiconductors in the periodic table II III IV V VI Be B C N O Mg Al Si P S Zn Ga Ge As Se Elemental semiconductors: C, Si, Ge (all group IV) Compound semiconductors: III-V: GaAs, GaN… II-VI: ZnO, ZnS,… Group-III and group-V atoms are “dopants”

Semiconductor essentials: impurities  Small impurities can dramatically change conductivity: – slight phosphorous contamination in silicon gives many extra free electrons in the material (one per P atom!) – slight aluminum contamination gives many extra holes (one per Al atom) P Al

Silicon dopants II III IV V VI Be B C N O Mg Al Si P S Zn Ga Ge As Se In Boron most widely used as p-type dopant; Phosphorous and arsenic both used widely as n-type dopant

Semiconductor essentials: n and p type n-type doped semiconductor e.g. silicon with phosphorus impurity electrons determine conductivity p-type doped semiconductor e.g. silicon with Al impurity holes determine conductivity p-n junction: current can only flow one way! Semiconductor diode

The field effect accumulation depletion inversion ++++++++ - - - - ----------

The MOS transistor ---------- SOURCE ---------- DRAIN

A MOS transistor layout source gate drain source gate drain (cross section) (top view) (cross section)

NMOS and PMOS transistors NMOS Free electron Free hole --- +++ Conducts at +VGB PMOS Conducts at -VGB NMOS + PMOS = CMOS

MOSFET operation (very basic) Vfb C accumulation VT depletion inversion V

Current through the MOS transistor inversion Channel charge: Q ~ (Vgs – VT) Channel current: I ~ (Vgs – VT) MOS transistor - simplistic I MOS transistor - real I Vgs VT Vgs VT

Concept of the floating-gate memory cell  MOS transistor: 1 fixed threshold voltage  Flash memory cell: VT can be changed by program/erase MOS transistor Floating gate transistor Id Id programming erasing Vgs VT Vgs

Floating gate transistor: principle  VT is shifted by injecting electrons into the floating gate;  It is shifted back by removing these electrons again. Floating gate • CMOS compatible technology! Control gate

Channel charge in floating gate transistors unprogrammed programmed Control gate Control gate Floating gate Floating gate silicon To obtain the same channel charge, the programmed gate needs a higher control-gate voltage than the unprogrammed gate

Logic “0” and “1” Reading a bit means: Id 1. Apply Vread on the control gate 2. Measure drain current Id of the floating-gate transistor ΔVT = -Q/Cpp When cells are placed in a matrix: drain lines Vread “1” → Iread >> 0 “0” → Iread = 0 Vgs Control gate lines

Switch Models for MOS transistors  n-Channel – Normally Open (NO) Switch Contact D G X X: • • X:X S Symbol Switch M odel: Simplifed Switch M odel  p-Channel – Normally Closed (NC) Switch Contact S G X • D Symbol X: • • Switch M odel X:X Simplified Switch M odel

Circuits of switch models  Series X: X X A ND Y Y: Y Series  Parallel X: X Y: Y X OR Y Parallel

Fully-complementary CMOS circuit  Circuit structure for fully-complementary CMOS gate logic 1 +V • • • F using p-type transistors (NC switches) • X1 X2 • • • • Xn • • • • • F using n-type transistors (NO switches) logic 0 General Structure F

CMOS circuit design example  Find a CMOS gate with the following function:  Beginning with F0, and using F F = X Z + Y Z = (X + Y)Z  The switch model circuit in terms of NO switches: F0 Circuit: F = X Y + Z X: X Y: Y Z: Z

CMOS circuit design example  The switch model circuit for F1 in terms of NC contacts is the dual of the switch model circuit for F0: X : X Y: Y Z: Z  The function for this circuit is: F1 Circuit: F = (X + Y) Z which is the correct F.

CMOS circuit design example(Cont.)  Replacing the switch models with CMOS transistors; note input Z must be used.

Technology parameters       Fan-in Fan-out Logic Levels Noise Margin Propagation Delay Power Dissipation 23

Technology parameters(Cont.)  Specific gate implementation technologies are characterized by the following parameters: – Fan-in – the number of inputs available on a gate – Fan-out – the number of standard loads driven by a gate output – Logic Levels – the signal value ranges for 1 and 0 on the inputs and 1 and 0 on the outputs (see Figure 1-1) – Noise Margin – the maximum external noise voltage superimposed on a normal input value that will not cause an undesirable change in the circuit output – Cost for a gate - a measure of the contribution by the gate to the cost of the integrated circuit – Propagation Delay – The time required for a change in the value of a signal to propagate from an input to an output – Power Dissipation – the amount of power drawn from the power supply and consumed by the gate

Fan-out  Fan-out can be defined in terms of a standard load – Example: 1 standard load equals the load contributed by the input of 1 inverter. – Transition time -the time required for the gate output to change from H to L, tHL, or from L to H, tLH – The maximum fan-out that can be driven by a gate is the number of standard loads the gate can drive without exceeding its specified maximum transition time

Cost  In an integrated circuit: – The cost of a gate is proportional to the chip area occupied by the gate – The gate area is roughly proportional to the number and size of the transistors and the amount of wiring connecting them – Ignoring the wiring area, the gate area is roughly proportional to the gate input count – So gate input count is a rough measure of gate cost  If the actual chip layout area occupied by the gate is known, it is a far more accurate measure

Propagation delay  Propagation delay is the time for a change on an input of a gate to propagate to the output.  Delay is usually measured at the 50% point with respect to the H and L output voltage levels.  High-to-low (tPHL) and low-to-high (tPLH) output signal changes may have different propagation delays.  High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input.  An HL input transition causes: – an LH output transition if the gate inverts and – an HL output transition if the gate does not invert.

Propagation delay (Cont.)  Propagation delays measured at the midpoint between the L and H values  What is the expression for the tPHL delay for: – a string of n identical buffers? – a string of n identical inverters?

Propagation delay Example OUT (volts) IN (volts)  Find tPHL, tPLH and tpd for the signals given t (ns) 1.0 ns per division

Delay models  Transport delay - a change in the output in response to a change on the inputs occurs after a fixed specified delay  Inertial delay - similar to transport delay, except that if the input changes such that the output is to change twice in a time interval less than the rejection time, the output changes do not occur. Models typical electronic circuit behavior, namely, rejects narrow “pulses” on the outputs

Delay models example A B A B: No Delay (ND) Transport Delay (TD) a b c d e Inertial Delay (ID) 0 2 4 6 8 10 12 14 16 Time (ns) Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns

Circuit delay  Suppose gates with delay n ns are represented for n = 0.2 ns, n = 0.4 ns, n = 0.5 ns, respectively: 0.2 0.4 0.5

Circuit delay(Cont.)  Consider a simple input multiplexer:  With function: – Y = A for S = 1 – Y = B for S = 0 2- A 0.2 S B  Glitch” is due to delay of inverter A B S S Y 0.4 0.5 0.4 Y

Fan-out and delay  The fan-out loading a gate’s output affects the gate’s propagation delay  Example: – One realistic equation for tpd for a NAND gate with 4 inputs is: tpd = 0.07 + 0.021 SL ns – SL is the number of standard loads the gate is driving, i. e., its fan-out in standard loads – For SL = 4.5, tpd = 0.165 ns  If this effect is considered, the delay of a gate in a circuit takes on different values depending on the circuit load on its output.

Cost/performance tradeoffs    Gate-Level Example: – NAND gate G with 20 standard loads on its output has a delay of 0.45 ns and has a normalized cost of 2.0 – A buffer H has a normalized cost of 1.5. The NAND gate driving the buffer with 20 standard loads gives a total delay of 0.33 ns – In which if the following cases should the buffer be added? 1. The cost of this portion of the circuit cannot be more than 2.5 2. The delay of this portion of the circuit cannot be more than 0.40 ns 3. The delay of this portion of the circuit must be less than 0.30 ns and the cost less than 3.0 Tradeoffs can also be accomplished much higher in the design hierarchy Constraints on cost and performance have a major role in making tradeoffs

thanks digital design

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