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1.digital design - combinational circuits

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Information about 1.digital design - combinational circuits
Design

Published on February 20, 2014

Author: mohamedaly71653

Source: slideshare.net

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Digital design Combinational circuits

Combinational circuits Combinational logic symbols  Common combinational logic systems have standard symbols called logic gates A B – Buffer, NOT – AND, NAND – OR, NOR 0 0 1 1 0 1 0 1 A*B A+B 0 0 0 1 0 1 1 1 Easy to implement with CMOS transistors (the switches we have available and use most)

Combinational logic symbols(Cont.)  NAND  NOR X Y X 0 0 1 1 X Y  XOR X Y X Y  XNOR X=Y X Y Z Z Y 0 1 0 1 Z 1 0 0 0 X 0 0 1 1 Z Z 1 1 1 0 X 0 0 1 1 Z Y 0 1 0 1 Y 0 1 0 1 Z 0 1 1 0 X xor Y = X Y' + X' Y X or Y but not both ("inequality", "difference") X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 1 X xnor Y = X Y + X' Y' X and Y are the same ("equality", "coincidence")

Example : two-bit comparator A B 0 0 N1 N2 A B C D LT EQ GT AB<CD AB=CD AB>CD 1 1 block diagram and truth table 0 0 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LT 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 EQ 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 GT 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 we'll need a 4-variable Karnaugh map for each of the 3 output functions

Example : two-bit comparator(Cont.) A B C D two alternative implementations of EQ with and without XOR EQ EQ XNOR is implemented with at least 3 simple gates

Example: 2x2-bit multiplier A1 A2 B1 B2 2x2-bit multiplier block diagram and truth table P1 P2 P4 P8 A2 A1 B2 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 1 B1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 P4 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 P2 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 4-variable K-map for each of the 4 output functions P1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1

Example : BCD increment by 1 I1 I2 I4 I8 BCD increment by 1 block diagram and truth table O1 O2 O4 O8 I8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 I4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 I2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 I1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 O8 0 0 0 0 0 0 0 1 1 0 X X X X X X O4 0 0 0 1 1 1 1 0 0 0 X X X X X X O2 0 1 1 0 0 1 1 0 0 0 X X X X X X 4-variable K-map for each of the 4 output functions O1 1 0 1 0 1 0 1 0 1 0 X X X X X X

Making connections  Direct point-to-point connections between gates – Wires we've seen so far  Route one of many inputs to a single output --multiplexer  Route a single input to one of many outputs --demultiplexer control multiplexer control demultiplexer 4x4 switch

Making connections(Cont.) Mux and de-mux  Switch implementation of multiplexers and demultiplexers – Can be composed to make arbitrary size switching networks – Used to implement multiple-source/multiple-destination interconnections A Y B Z A Y B Z

Making connections(Cont.) Mux and de-mux (Cont.)  Uses of multiplexers/de-multiplexers in multipoint connections A0 A1 B0 Sa MUX B1 MUX A Sb multiple input sources B Sum Ss DEMUX S0 S1 multiple output destinations

Multiplexers/Selectors  Multiplexers/Selectors: general concept – 2n data inputs, n control inputs (called "selects"), 1 output – Used to connect 2n points to a single point – Control signal pattern forms binary index of input connected to output A 0 1 Z = A' I0 + A I1 Z I0 I1 functional form logical form two alternative forms for a 2:1 Mux truth table I1 0 0 0 0 1 1 1 1 I0 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 Z 0 0 1 0 0 1 1 1

Multiplexers/Selectors(Cont.) B A S I0 I1 I2 I3 I4 I5 I6 I7 C I0 I1 2:1 mux A Z I0 I1 I2 I3 4:1 mux Z A B 8:1 mux A B C A31:0 B31:0 S C Z

Multiplexers/Selectors(Cont.) Gate level implementation of muxes • 2:1 mux • 4:1 mux

Multiplexers/Selectors(Cont.) Cascading multiplexers alternative implementation I0 I1 I0 I1 I2 I3 4:1 mux I4 I5 I6 I7 4:1 mux 2:1 mux B C I2 I3 8:1 mux 2:1 mux 2:1 mux A I4 I5 2:1 mux I6 I7 Z 8:1 mux 4:1 mux 2:1 mux C A B Z

Multiplexers/Selectors(Cont.) Multiplexers as general-purpose logic 1 0 1 0 0 0 1 1  Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1) Example : F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC 0 = A'B'(C') + A'B(C') + AB'(0) + AB(1) 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B C F A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 1 0 1 0 0 0 1 1 C' C' 0 1 1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A C' C' 0 1 B C 0 1 4:1 MUX 2 3 S1 S0 A B F F

Multiplexers/Selectors(Cont.) Multiplexers as general-purpose logic(Cont.)  Generalization I0 . . . 0 0 0 1 1 . . . . 1 0 1 0 1 0 single mux data variable . . . In-1 In . n-1 mux control variables I1 F In In' 1 four possible configurations of truth table rows can be expressed as a function of In  Example: F(A,B,C,D) implemented by an 8:1 1 0 MUX A D 1 1 1 0 1 1 C 0 0 0 1 1 0 1 0 1 1 0 choose A,B,C as control variables D multiplexer implementation 0 1 D’ D D’ D’ 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 B A B C

De-multiplexers/Decoders  Decoders/de-multiplexers: general concept – Single data input, n control inputs, 2n outputs Decoder   N inputs 2N outputs Enable – Control inputs (called “selects” (S)) represent binary index of output to which the input is connected 3:8 Decoder: – Data input usually called “enable” (G) O0 = G  S2’  S1’  S0’ O1 = G  S2’  S1’  S0 1:2 Decoder: O0 = G  S’ O1 = G  S 2:4 Decoder: O0 = G  S1’  O1 = G  S1’  O2 = G  S1  O3 = G  S1  S0’ S0 S0’ S0 O2 O3 O4 O5 O6 O7 = = = = = = G G G G G G       S2’ S2’ S2 S2 S2 S2       S1 S1 S1’ S1’ S1 S1  S0’  S0  S0’  S0  S0’  S0

De-multiplexers/Decoders(Cont.) Gate level implementation of de-multiplexers  1:2 Decoders active-high enable G O0 S O1 O1 O0 active-high enable O0 S  2:4 Decoders G active-low enable G O1 G O0 active-low enable O1 O2 O3 S1 S0 O2 O3 S1 S0

De-multiplexers/Decoders(Cont.) Cascading decoders F 0 2:4 DEC 1 2 S1 S0 3 A B 0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 C D A'B'C'D'E' ABCDE E 5:32 DEC 0 1 2 3:8 DEC3 4 5 6 7 S2 S1 S0 0 1 2 3:8 DEC 3 4 5 6 7 S2 S1 S0 C D E A'BC'DE' AB'C'D'E' AB'CDE

De-multiplexers/Decoders(Cont.) De-multiplexers as general-purpose logic “1” 0 1 2 3 3:8 DEC 4 5 6 7 S2 S1 S0 A B A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC C  Example -F1 = A' B C' D + Enable A' B' C D + A B C D -F2 = A B C' D’ + A B C -F3 = (A' + B' + C' + D') demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) 0 1 2 3 4 5 6 4:16 7 DEC 8 9 10 11 12 13 14 15 A B C D A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD F1 F2 F3

Combinational circuit analysis

Tri-state gates  Third value – Logic values: “0”, “1” – Don't care: “X” (must be 0 or 1 in real circuit!) – Third value or state: “Z” — high impedance, infinite R, no connection  Tri-state gates – – – – – OE Additional input – output enable (OE) In Output values are 0, 1, and Z When OE is high, the gate functions normally When OE is low, the gate is disconnected from wire at output Allows more than one gate to be connected to the same output wire • As long as only one has its output enabled at any one time (otherwise, sparks could fly) non-inverting tri-state buffer In X 0 1 OE 0 1 1 Out Z 0 1 In OE Out Out 100

Tri-state gates(Cont.) Tri-state and multiplexing  When Using tri-state logic – (1) Never more than one "driver" for a wire at any one time (pulling high and low at same time can severely damage circuits) – (2) Only use value on wire when its being driven (using a floating value may cause failures)  Using tri-state gates to Implement an economical multiplexer F Input0 OE Input1 OE when Select is high Input1 is connected to F when Select is low Input0 is connected to F this is essentially a 2:1 mux Select Mux

Tri-state gates(Cont.) Bi-direction circuit X Y C Bi-direction circuit

Open-collector gates and wired-AND  Open collector: another way to connect gate outputs to same wire – Gate only has the ability to pull its output low – Cannot actively drive wire high (default – pulled high through resistor)  Wired-AND can be implemented with open collector logic – – – – If A and B are "1", output is actively pulled low If C and D are "1", output is actively pulled low If one gate output is low and the other high, then low wins If both outputs are "1", the wire value "floats", pulled high by resistor • Low to high transition usually slower than if gate pulling high – Hence, the two NAND functions are ANDed together open-collector NAND gates with ouputs wired together using "wired-AND" to form (AB)'(CD)'

Relationship among representations  Theorem: Any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using AND, OR, NOT. unique ? not unique Boolean Expression [convenient for manipulation] Truth Table ? gate representation (schematic) not unique [close to implementaton] How do we convert from one to the other?

thanks digital design

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