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Digital design HLL Program Asm Lang. Pgm Machine Lang. pgm foo.c foo.s foo.exe foo.o Software Hardware Instruction Set Architecture Machine Organization Instr. Set Proc. I/O system Datapath & Control Digital Design Circuit Design Layout & fab Semiconductor Materials

Digital design(Cont.) Pgm Language Asm / Machine Lang Instruction Set Arch Machine Organization HDL FlipFlops Gates Circuits Devices Transistor Physics Transfer Function Deep Digital Design Experience Fundamentals of Boolean Logic Synchronous Circuits Finite State Machines Timing & Clocking Controller Design Arithmetic Units Bus Design Encoding, Framing Testing, Debugging Hardware Architecture HDL, Design Flow (CAD)

Combinational vs. sequential digital circuits A simple model of a digital system is a unit with inputs and outputs: inputs system outputs Combinational means "memory-less" – a digital circuit is combinational if its output values only depend on its input values Sequential systems – Exhibit behaviors (output values) that depend not only on the current input values, but also on previous input values In reality, all real circuits are sequential – The outputs do not change instantaneously after an input change – Why not, and why is it then sequential? A fundamental abstraction of digital design is to reason (mostly) about steadystate behaviors – Look at outputs only after sufficient time has elapsed for the system to make its required changes and settle down

Synchronous sequential digital systems Outputs of a combinational circuit depend only on current inputs – After sufficient time has elapsed Sequential circuits have memory – Even after waiting for the transient activity to finish The steady-state abstraction is so useful that most designers use a form of it when constructing sequential circuits: – Memory of a system is represented as its state – Changes in system state are only allowed to occur at specific times controlled by an external periodic clock – Clock period is the time that elapses between state changes it must be sufficiently long so that the system reaches a steady-state before the next state change at the end of the period

Digital design Motivation design example

Door combination lock Punch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset Inputs: sequence of input values, reset Outputs: door open/close Memory: must remember combination or always have it available as an input

Software implementation integer combination_lock ( ) { integer v1, v2, v3; integer error = 0; static integer c[3] = 3, 4, 2; while (!new_value( )); v1 = read_value( ); if (v1 != c[1]) then error = 1; while (!new_value( )); v2 = read_value( ); if (v2 != c[2]) then error = 1; while (!new_value( )); v3 = read_value( ); if (v2 != c[3]) then error = 1; if (error == 1) then return(0); else return (1); }

Hardware implementation Encoding: – how many bits per input value? – how many values in sequence? – how do we know a new input value is entered? – how do we represent the states of the system? Behavior: – clock wire tells us when it’s ok to look at inputs (i.e., they have settled after change) – sequential: sequence of values must be clock entered – sequential: remember if an error occurred – finite-state specification new value reset state open/closed

Hardware implementation(Cont.) Abstract control Finite-state diagram – States: 5 states • represent point in execution of machine • each state has outputs – Transitions: 6 from state to state, 5 self transitions, 1 global • changes of state occur when clock says it’s ok • based on value of inputs ERR – Inputs: reset, new, results of comparisons – Output: open/closed C1!=value & new S1 reset closed not new C1=value & new S2 closed not new C2=value & new closed C2!=value & new S3 closed not new C3!=value & new C3=value & new OPEN open

Hardware implementation(Cont.) Data-path vs. control Internal structure – data-path • storage for combination • comparators – control • finite-state machine controller • control for data-path • state changes controlled by clock new equal reset value C1 C2 multiplexer C3 mux control controller clock comparator equal open/closed

Hardware implementation(Cont.) Finite-state machine Finite-state machine – refine state diagram to include internal structure ERR closed not equal & new S1 reset closed mux=C1 not new S2 not equal & new S3 closed closed not new not new not equal & new equal mux=C2 equal mux=C3 equal & new & new & new OPEN open

Hardware implementation(Cont.) Finite-state machine(Cont.) Finite-state machine – generate state table (much like a truth-table) reset 1 0 0 0 0 0 0 0 0 0 0 0 new – 0 1 1 0 1 1 0 1 1 – – equal – – 0 1 – 0 1 – 0 1 – – state – S1 S1 S1 S2 S2 S2 S3 S3 S3 OPEN ERR next state S1 S1 ERR S2 S2 ERR S3 S3 ERR OPEN OPEN ERR mux C1 C1 – C2 C2 – C3 C3 – – – – open/closed closed closed closed closed closed closed closed reset closed closed open open closed ERR closed not equal & new S2 S1 closed mux=C1 not new equal & new closed mux=C2 not new equal & new not equal & new S3 closed mux=C3 not new not equal & new equal & new OPEN open

Hardware implementation(Cont.) Encoding Encode state table – state can be: S1, S2, S3, OPEN, or ERR • needs at least 3 bits to encode: 000, 001, 010, 011, 100 • and as many as 5: 00001, 00010, 00100, 01000, 10000 • choose 4 bits: 0001, 0010, 0100, 1000, 0000 – output mux can be: C1, C2, or C3 • needs 2 to 3 bits to encode • choose 3 bits: 001, 010, 100 – output open/closed can be: open or closed • needs 1 or 2 bits to encode • choose 1 bits: 1, 0

Hardware implementation(Cont.) Encoding(Cont.) Encode state table – state can be: S1, S2, S3, OPEN, or ERR • choose 4 bits: 0001, 0010, 0100, 1000, 0000 – output mux can be: C1, C2, or C3 • choose 3 bits: 001, 010, 100 – output open/closed can be: open or closed • choose 1 bits: 1, 0 reset 1 0 0 0 0 0 0 0 0 0 0 0 new – 0 1 1 0 1 1 0 1 1 – – equal – – 0 1 – 0 1 – 0 1 – – state – 0001 0001 0001 0010 0010 0010 0100 0100 0100 1000 0000 next state 0001 0001 0000 0010 0010 0000 0100 0100 0000 1000 1000 0000 mux 001 001 – 010 010 – 100 100 – – – – open/closed 0 0 0 good choice of encoding! 0 0 mux is identical to 0 last 3 bits of state 0 0 open/closed is 0 identical to first bit 1 of state 1 0

Hardware implementation(Cont.) Controller implementation Implementation of the controller new mux control equal special circuit element, called a register, for remembering inputs when told to by clock reset controller clock new equal reset open/closed mux control comb. logic state open/closed clock

Hardware implementation(Cont.) Design hierarchy system control data-path code registers multiplexer comparator register state registers logic switching networks combinational logic

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